Design and implementation of convolution neural network accelerator for Winograd algorithm based on FPGA

NIU Zhao-xu; SUN Hai-jiang

doi:10.37188/CJLCD.2023-0013

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Design and implementation of convolution neural network accelerator for Winograd algorithm based on FPGA

Object Detection and Recognition | 更新时间：2023-11-03

- Design and implementation of convolution neural network accelerator for Winograd algorithm based on FPGA
- Chinese Journal of Liquid Crystals and Displays Vol. 38, Issue 11, Pages: 1521-1530(2023)
- 作者机构：
  
  1.中国科学院长春光学精密机械与物理研究所，吉林长春 130033
  2.中国科学院大学，北京 100049
- 作者简介：
- 基金信息：
  
  Jilin Province Science and Technology Development Plan(20200404155YY)
- DOI：10.37188/CJLCD.2023-0013
  CLC：
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NIU Zhao-xu, SUN Hai-jiang. Design and implementation of convolution neural network accelerator for Winograd algorithm based on FPGA. [J]. Chinese Journal of Liquid Crystals and Displays 38(11):1521-1530(2023)
DOI：

NIU Zhao-xu, SUN Hai-jiang. Design and implementation of convolution neural network accelerator for Winograd algorithm based on FPGA. [J]. Chinese Journal of Liquid Crystals and Displays 38(11):1521-1530(2023) DOI： 10.37188/CJLCD.2023-0013.

摘要

为实现卷积神经网络在低功耗、边缘计算等场景中的加速计算，设计了一种基于现场可编程门阵列（FPGA）的Winograd算法卷积神经网络加速器。首先，将图像数据和权重数据量化为8位定点数，并设计了硬件卷积计算过程中的量化流程，提升了数据传输速度和计算速度。接着，设计了输入数据缓存复用模块，将多输入通道数据融合后传输，复用了行重叠数据。然后设计了Winograd流水线卷积模块，实现列数据的组合复用，从而最大化重用了片上数据，降低了片上数据存储的占用和带宽压力。最后将加速器在Xilinx的ZCU104开发板上部署。经过实验验证，加速器的卷积层计算性能达到354.5 GOPS，片上DSP计算效率达到0.69，与相关研究相比，实现了1.6倍以上的提升。该加速器能够以高能效比完成基于VGG-16网络的遥感图像分类任务。

Abstract

In order to realize the acceleration of convolutional neural network in low-power， edge computing and other scenarios， a Winograd algorithm convolutional neural network accelerator based on field programmable gate array （FPGA） is designed. Firstly， the image data and weight data are quantized into 8-bit fixed-point numbers， and the quantization process in the hardware convolution calculation process is designed to improve data transmission speed and calculation speed. Secondly， the input data buffer multiplexing module is designed， which fuses the data of multiple input channels and transmits them， reusing the row overlapping data. Then， the Winograd pipeline convolution module is designed to realize the combined reuse of column data， so as to maximize the reuse of data on chip and reduce the occupation of data storage on chip and bandwidth pressure. Finally， the accelerator is deployed on the ZCU104 development board of Xilinx. Experimental verification shows that the convolution layer computing performance of accelerator reaches to 354.5 GOPS， and the on-chip DSP computing efficiency reaches to 0.69， which is more than 1.6 times higher than relevant research. The accelerator can complete remote sensing image classification task based on VGG-16 network with high energy efficiency ratio.

关键词

卷积神经网络现场可编程门阵列Winograd算法流水线并行计算

Keywords

convolution neural networkfield programmable gate arraywinograd algorithmassembly lineparallel computing

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