Analysis and optimization of energy efficiency for silicon-based chips

XUE Bosen; ZHA Zhengtao; MU Quanquan; WANG Qidong; PENG Zenghui

doi:10.37188/CJLCD.2026-0078

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Analysis and optimization of energy efficiency for silicon-based chips

Device Physics and Device Preparation | 更新时间：2026-09-12

- Analysis and optimization of energy efficiency for silicon-based chips
- Chinese Journal of Liquid Crystals and Displays Vol. 41, Issue 6, Pages: 783-792(2026)
- 作者机构：
  
  1.中国科学院长春光学精密机械与物理研究所，吉林长春 130033
  2.中国科学院大学材料科学与光电工程中心，北京 100049
  3.光学系统先进制造全国重点实验室，吉林长春 130033
- 作者简介：
- 基金信息：
  
  National Key R&D Program of China(2025YFH0100600)
- DOI：10.37188/CJLCD.2026-0078
  CLC： O436.1
- CSTR：32172.14.CJLCD.2026-0078
- Received：02 May 2026，
  
  Revised：2026-05-16，
  
  Published：06 June 2026
- 稿件说明：
移动端阅览
XUE Bosen, ZHA Zhengtao, MU Quanquan, et al. Analysis and optimization of energy efficiency for silicon-based chips[J]. Chinese Journal of Liquid Crystals and Displays, 2026, 41(6): 783-792.
DOI：

XUE Bosen, ZHA Zhengtao, MU Quanquan, et al. Analysis and optimization of energy efficiency for silicon-based chips[J]. Chinese Journal of Liquid Crystals and Displays, 2026, 41(6): 783-792. DOI： 10.37188/CJLCD.2026-0078. CSTR： 32172.14.CJLCD.2026-0078.

摘要

为解决小像素尺寸硅基芯片能量效率低、标量衍射理论计算精度不足的问题，本文围绕硅基芯片能量效率开展精确计算与优化研究。分别采用标量衍射理论与时域有限差分（Finite-Difference Time-Domain，FDTD）方法对硅基芯片的能量效率展开计算，并搭建532 nm激光测试系统进行实验验证。选用TiO

/SiO

材料设计

/4型多层介质高反膜，通过FDTD仿真分析了膜系周期数、工作波长对能量效率优化规律的影响。研究结果表明，对于当前常见像素尺寸（像素周期2~8 μm）的硅基芯片，采用FDTD方法计算得到的能量效率与实验结果的绝对误差小于1%；镀多层介质膜可以有效提升芯片能量效率，当反射膜周期单元数达到5时，各像素尺寸芯片在450~625 nm波长范围内能量效率均达95%以上。

Abstract

To solve the problems of low energy efficiency of small-pixel silicon-based chips and insufficient calc

ulation accuracy of the scalar diffraction theory， this study conducts precise calculation and optimization research on the energy efficiency of silicon-based chips. The energy efficiency of silicon-based chips is calculated using both the scalar diffraction theory and the Finite-Difference Time-Domain（FDTD） method， and an experimental verification is carried out by building a 532 nm laser testing system. A

/4-type multilayer dielectric high-reflection coating is designed using TiO

/SiO

materials， and the optimization rules of the number of coating periods and operating wavelength on energy efficiency are analyzed via FDTD simulations. The research results show that for the currently common silicon-based chips with small pixel sizes（pixel period： 2~8 μm）， the absolute error between the energy efficiency calculated by the FDTD method and the experimental results is less than 1%. Coating the multilayer dielectric film can effectively improve the energy efficiency of the chip； when the number of reflective coating periods reaches 5， the energy efficiency of chips of various pixel sizes exceeds 95% in the wavelength range of 450~625 nm.

关键词

Keywords

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