Design of heterogeneous FPGA hardware accelerator based on CNN
Circuit Design|更新时间:2025-03-06
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Design of heterogeneous FPGA hardware accelerator based on CNN
“In the field of hardware design, experts have proposed a heterogeneous embedded system design based on SoC, which effectively improves the power efficiency of CNN networks and provides a new solution for energy-efficient hardware design.”
Chinese Journal of Liquid Crystals and DisplaysVol. 40, Issue 3, Pages: 448-456(2025)
作者机构:
1.中国科学院 长春光学精密机械与物理研究所,吉林 长春 130033
2.中国科学院大学,北京 100049
3.中国科学院 天基动态快速光学成像技术重点实验室,吉林 长春 130033
作者简介:
基金信息:
Qian Xuesen Laboratory of Space Technology Innovation Workstation Development Foundation(GZZKFJJ2020003)
JI Haolin, XU Wei, PIAO Yongjie, et al. Design of heterogeneous FPGA hardware accelerator based on CNN[J]. Chinese journal of liquid crystals and displays, 2025, 40(3): 448-456.
DOI:
JI Haolin, XU Wei, PIAO Yongjie, et al. Design of heterogeneous FPGA hardware accelerator based on CNN[J]. Chinese journal of liquid crystals and displays, 2025, 40(3): 448-456. DOI: 10.37188/CJLCD.2024-0198. CSTR: 32172.14.CJLCD.2024-0198.
Design of heterogeneous FPGA hardware accelerator based on CNN