周期分散刷新算法在SDRAM控制器中的应用

武春锋; 王志乾; 刘绍锦; 刘玉生

doi:10.3788/YJYXS20183305.0405

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周期分散刷新算法在SDRAM控制器中的应用

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- 周期分散刷新算法在SDRAM控制器中的应用
- Application of periodic and distributed refresh algorithm in SDRAM controller
- 液晶与显示 2018年33卷第5期页码：405-411
- 作者机构：
  
  1.中国科学院长春光学精密机械与物理研究所, 吉林长春 130033
  2.中国科学院大学, 北京 100049
- 作者简介：
  
  [ "武春锋(1992-), 男, 河南许昌人, 硕士, 研究方向为FPGA数字系统设计。E-mail:15526647839@163.com" ]
  [ "王志乾(1969-), 男, 吉林省吉林市人, 研究员, 博士生导师, 研究方向为光电测量、数字信号处理。E-mail:zhiqian_wang@sina.com" ]
- 基金信息：
  
  吉林省重点科技攻关项目(20170204050GX);Key Science and Technology Foundation of Jilin Province, China(20170204050GX)
- DOI：10.3788/YJYXS20183305.0405
  中图分类号： TP368.1
- 收稿日期：2017-12-27，
  
  录用日期：2018-2-1，
  
  纸质出版日期：2018-05
- 稿件说明：
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武春锋, 王志乾, 刘绍锦, 等. 周期分散刷新算法在SDRAM控制器中的应用[J]. 液晶与显示, 2018,33(5):405-411.

Chun-feng WU, Zhi-qian WANG, Shao-jin LIU, et al. Application of periodic and distributed refresh algorithm in SDRAM controller[J]. Chinese journal of liquid crystals and displays, 2018, 33(5): 405-411.
武春锋, 王志乾, 刘绍锦, 等. 周期分散刷新算法在SDRAM控制器中的应用[J]. 液晶与显示, 2018,33(5):405-411. DOI： 10.3788/YJYXS20183305.0405.

Chun-feng WU, Zhi-qian WANG, Shao-jin LIU, et al. Application of periodic and distributed refresh algorithm in SDRAM controller[J]. Chinese journal of liquid crystals and displays, 2018, 33(5): 405-411. DOI： 10.3788/YJYXS20183305.0405.

摘要

针对SDRAM控制器的自动刷新指令控制方法，提出了一种周期分散刷新算法。首先，使用Verilog HDL编写SDRAM控制器。在读写过程，根据SDRAM时钟频率和存储阵列行数，确定连续读/写的次数

。连续

次读/写操作后，控制器发出一次自动刷新指令。在非读写过程，根据状态机长期处于空闲状态的特点，控制器定时发出自动刷新请求，从而周期地发出自动刷新指令。然后，基于光电测量系统对算法进行验证。实验结果表明控制器周期、及时、准确地发出了自动刷新指令，读写指令执行效率提高了0.39%。该算法解决了自动刷新指令滞后的问题，提高了读写指令执行效率，具有良好的移植性。

Abstract

Aiming at the control method of Auto_Refresh instruction in SDRAM controller

a periodic and distributed refresh algorithm is proposed. First

A SDRAM controller is compiled by Verilog HDL. In reading or writing process

the continuous times of reading or writing is confirmed by SDRAM clock frequency and the row number of L-BANK. An Auto_Refresh instruction is given after

reading or

writing instructions. Because FSM is almost always in the state of IDLE in the process after reading and writing

Auto_Refresh instruction is given periodically. Then

the Photoelectric Measurement System is used for experimental verification. The experimental results show that SDRAM controller can give Auto_Refresh periodically

timely and accurately

and the execution efficiency of reading and writing instructions is improved by 0.39%. This algorithm solves the problem of Auto_Refresh instruction lagged behind

improves the execution efficiency of reading and writing instructions

and has good portability.

关键词

Keywords

references

ISLAM A, ARAFATH Y, HASAN J. Design of DDR4 SDRAM controller[C]// Proceedings of 2014 International Conference on Electrical and Computer Engineering . Dhaka, Bangladesh: IEEE, 2014: 148-151.

陈东成, 胡敬营, 吕卫国, 等.基于IP核的多接口LCD控制器的设计及实现[J].液晶与显示, 2017, 32(2):117-123.

CHEN D C, HU J Y, LV W G, et al . Design and implementation of muti-interface LCD controller based on IP cores[J]. Chinese Journal of Liquid Crystals and Displays , 2017, 32(2):117-123. (in Chinese)

夏巧桥, 汪鼎文, 张立国, 等.高速多通道遥感相机快视系统的实现[J].光学精密工程, 2013, 21(1):158-166.

XIA QQ, WANG D W, ZHANG L G, et al . Realization of fast-view system for high-speed multi-channel remote sensing camera[J]. Optics and Precision Engineering , 2013, 21(1):158-166. (in Chinese)

余辉龙, 何昕, 魏仲慧, 等.应用NAND型闪存的高速大容量图像存储器[J].光学精密工程, 2009, 17(10):2548-2554.

YU H L, HE X, WEI Z H, et al . High speed and high capacity image recorder based on NAND flash[J]. Optics and Precision Engineering , 2009, 17(10):2548-2554. (in Chinese)

WANG Y, HAN Y H, WANG C, et al . Retention-aware DRAM Assembly and repair for future FGR memories[J]. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems , 2017, 36(5):705-718.

徐启明, 张启衡, 陈强.基于DDR模组阵列的超高速数字图像存储技术[J].光学精密工程, 2009, 17(1):231-235.

XU Q M, ZHANG Q H, CHEN Q. Ultra high-speed digital image storage technology based on DDR dual in-line memory module array[J]. Optics and Precision Engineering , 2009, 17(1):231-235. (in Chinese)

舒立. 高性能SDRAM控制器设计及软硬件结合测试[D]. 成都: 电子科技大学, 2012.

SHU L. Design of SDRAM controller and testing by the combination of hardware and software [D]. Chengdu: University of Electronic Science and Technology of China, 2012. (in Chinese)

韦喜波. DDR SDRAM控制器的设计与验证[D]. 哈尔滨: 哈尔滨工业大学, 2009.

WEI X B. Design and verification of DDR SDRAM controller[D]. Harbin: Harbin Institute of Technology, 2009. (in Chinese)

王斌, 熊志辉, 陈立栋, 等.具有时间隐藏特性的数据块读写SDRAM控制器[J].计算机工程, 2009, 35(4):244-246.

WAGN B, XIONG Z H, CHEN L D, et al . SDRAM controller with time-hiding feature for data block access[J]. Computer Engineering , 2009, 35(4):244-246. (in Chinese)

董振兴, 朱岩, 许志宏, 等.星载存储器吞吐率瓶颈与高速并行缓存机制[J].哈尔滨工业大学学报, 2017, 49(11):52-59.

DONG Z X, ZHU Y, XU Z H, et al . Bottleneck analysis of spaceborne memory throughput and high-speed parallel caching mechanism design[J]. Journal of Harbin Institute of Technology , 2017, 49(11):52-59. (in Chinese)

王明富, 杨世洪, 吴钦章.大面阵CCD图像实时显示系统的设计[J].光学精密工程, 2010, 18(9):2053-2059.

WANG M F, YANG S H, WU Q Z. Design of large-array CCD real-time display system[J]. Optics and Precision Engineering , 2010, 18(9):2053-2059. (in Chinese)

马冬雪. 基于FPGA的图像采集存储系统设计与实现[D]. 沈阳: 东北大学, 2010.

MA D X. Design and implementation of image aciquition and storage system based on FPGA[D]. Shenyang: Northeastern University, 2010. (in Chinese)

罗杰.Verilog HDL与FPGA数字系统设计[M].北京:机械工业出版社, 2015.

LUO J. Design of Verilog HDL and FPGA Digital System [M]. Beijing:China Machine Press, 2015. (in Chinese)

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