基于FPGA的红外相机时序构造设计

韩红霞; 孙航; 曹立华

doi:10.3788/YJYXS20142903.0370

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基于FPGA的红外相机时序构造设计

器件物理及器件制备技术 | 更新时间：2020-08-12

- 基于FPGA的红外相机时序构造设计
- IR camera sequence construction design based on FPGA
- 液晶与显示 2014年29卷第3期页码：370-376
- 作者机构：
  
  中国科学院长春光学精密机械与物理研究所,吉林长春,中国,130033
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20142903.0370
  中图分类号：
- 收稿日期：2013-02-23，
  
  修回日期：2013-08-29，
  
  网络出版日期：2013-09-09，
  
  纸质出版日期：2014-04-25
- 稿件说明：
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韩红霞, 孙航, 曹立华. 基于FPGA的红外相机时序构造设计[J]. 液晶与显示, 2014,29(3): 370-376

HAN Hong-xia, SUN Hang, CAO Li-hua. IR camera sequence construction design based on FPGA[J]. , 2014,29(3): 370-376
韩红霞, 孙航, 曹立华. 基于FPGA的红外相机时序构造设计[J]. 液晶与显示, 2014,29(3): 370-376 DOI： 10.3788/YJYXS20142903.0370.

HAN Hong-xia, SUN Hang, CAO Li-hua. IR camera sequence construction design based on FPGA[J]. , 2014,29(3): 370-376 DOI： 10.3788/YJYXS20142903.0370.

摘要

为节省光电跟踪测量设备中红外相机的使用次数和时间，以延长设备的使用年限，设计了基于FPGA的红外相机时序构造系统，产生与相机时序一致的输出信号，在项目调试时代替红外相机为图像处理等后续系统提供数据源。设计采用FPGA编程和SignaTap工具相结合的方法测量项目所用红外相机的真实时序，并形成详细的时序记录文件，在此基础上采用Verilog语言编程，形成与相机时序一致的输出信号，其中包括时钟信号CCDCLK、场同步信号FVAL、行同步信号LVAL及数据有效信号DVAL，相机数据CCDDATA采用渐变数代替。试验中，产生帧频为50 Hz，像素时钟为40 MHz，靶面尺寸为640512的相机输出信号，提供给图像传输、图像处理等后续系统作为数据源。实验证明：产生的构造时序信号与相机时序一致，在调试试验中应用状况良好，在项目调试时可以代替红外相机，很大程度地节省了红外相机的开机时间，为项目节约了开发成本，具有较强的工程实践意义。

Abstract

To save the use time of the IR camera in the Optic-Electronic tracking and measure equipment

the IR camera sequence construction system based on FPGA has been designed. The system can generate the simulated output signal of the IR camera

supplying the data source for the continuous image processing system when the equipment debug is done. In the system design

the FPGA programming and SignalTap tool was combined to measure the true sequence of the practical IR camera

and the detailed record file was generated. Based on the sequence file

the verilog language was used to program and the construction signal was output

which includes the clock signal CCDCLK

frame signal FVAL

row signal LVAL and data valid signal DVAL

the camera data CCDDATA was applied with the incremental number. In the experiment

the camera simulated signal was generated

the FVAL signal was 50 Hz

the CCDCLK signal was 40 MHz

and the image size was 640512

the constructed data was supplied to the continuous system as the data source. The experiment proved that the constructed sequence signal was totally coherent with the practical IR camera

and the system ran well in the equipment debug period

the sequence constructed board could replace the camera when debugging. The IR camera sequence construction design makes the use time of the IR camera be saved

and item cost be economized. So the system design bears practical engineer meaning.

关键词

Keywords

references

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