The input macro block was used in the design of a signal receiver that turned LVDS signal into CMOS signal. The terminal resistors were analyzed; two methods of using terminal resistance were illustrated. The principle and the using of FPGA embedded resis-tance were emphatically analyzed. DDR technology was used

the method of using 3.5 times clock frequency to process 7 times data was researched and the frequency of data process was reduced. A serial to parallel converter was designed by using the data buffer. The method of data alignment and the two signal mapping formats supported by OpenLDI were analyzed. The data that conforms to the two standard data mapping format was output by using a data distributor. Combining with the characteristics of the Xilinx's FPGA clock processing macro block

the method of the clock recovering was researched. The periodic constraints

the special constraints

and the location constraints were used to improve the reliability of system. In order to improve the signal integrity of the whole circuit board and reduce the complexity of PCB layout

the method of inverting LVDS signals was studied.