基于以顶层ITO为像素电极设计的产品工艺优化

吕艳明; 操彬彬; 栗芳芳; 安晖; 叶成枝; 李法杰; 杨增乾; 彭俊林; 冯耀耀; 刘增利; 陆相晚; 李恒滨

doi:10.3788/YJYXS20203503.0219

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基于以顶层ITO为像素电极设计的产品工艺优化

材料与器件 | 更新时间：2020-08-12

- 基于以顶层ITO为像素电极设计的产品工艺优化
- Process optimization based on products of pixel top design
- 液晶与显示 2020年35卷第3期页码：219-226
- 作者机构：
  
  合肥鑫晟光电科技有限公司, 安徽合肥 230001
- 作者简介：
  
  [ "吕艳明(1986-), 男, 内蒙古开鲁县人, 学士, 2009年于安徽大学获得学士学位, 主要从事液晶显示器TFT工艺相关的技术研发工作。E-mail:lvyanming@boe.com.cn" ]
- 基金信息：
- DOI：10.3788/YJYXS20203503.0219
  中图分类号： TN141.9
- 收稿日期：2019-08-30，
  
  修回日期：2019-11-15，
  
  录用日期：2019-11-15，
  
  纸质出版日期：2020-03-05
- 稿件说明：
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吕艳明, 操彬彬, 栗芳芳, 等. 基于以顶层ITO为像素电极设计的产品工艺优化[J]. 液晶与显示, 2020,35(3):219-226.

Yan-ming LYU, Bin-bin CAO, Fang-fang LI, et al. Process optimization based on products of pixel top design[J]. Chinese journal of liquid crystals and displays, 2020, 35(3): 219-226.
吕艳明, 操彬彬, 栗芳芳, 等. 基于以顶层ITO为像素电极设计的产品工艺优化[J]. 液晶与显示, 2020,35(3):219-226. DOI： 10.3788/YJYXS20203503.0219.

Yan-ming LYU, Bin-bin CAO, Fang-fang LI, et al. Process optimization based on products of pixel top design[J]. Chinese journal of liquid crystals and displays, 2020, 35(3): 219-226. DOI： 10.3788/YJYXS20203503.0219.

摘要

HADS产品通常使用有机膜材料来减小寄生电容，以实现高像素密度（PPI）显示。本文对如何改善以顶层ITO为像素电极（Pixel Top）设计的有机膜产品的公共电极ITO与数据线间短路（DCS）不良进行了工艺优化研究。首先，通过显微镜、聚焦离子束对HADS有机膜产品DCS不良发生机理进行了分析，进而提出了第一钝化绝缘层刻蚀工序省略、保留第一钝化绝缘层至公共电极与像素电极间第二钝化绝缘层刻蚀时进行“一步刻蚀”的工艺流程变更改善方案。针对新工艺流程验证中TFT栅极过孔处第一钝化绝缘层出现的底切不良，通过调整等离子增强化学气相沉积成膜参数改善第一钝化绝缘层膜质，并选取最优成膜条件进一步调整干法刻蚀参数改善刻蚀形貌，获得了优良的栅极过孔刻蚀坡度角。优化后的“一步刻蚀”工艺进行的TFT基板，其栅极过孔第一钝化绝缘层坡度角小于40°，与栅极绝缘层间无明显刻蚀台阶。量产验证有机膜缺失导致的DCS发生率降为0。通过优化工艺，在降低产品不良率的同时还减少了工艺步骤，提升了产能。

Abstract

HADS products typically use organic film materials to reduce parasitic capacitance for high PPI display. In this paper

the process optimization of the common electrode ITO and the data line short-circuit defect of the organic film product designed by the top ITO for the pixel electrode (Pixel Top) is improved. Firstly

the mechanism of DCS failure of HADS organic film products is analyzed by microscope and Focused Ion beam. A 'one-step etch' process variation improvement scheme which skips the PVX1 etch step and retains PVX1 until PVX2 etch is proposed. Aiming at the problem of PVX1 layer undercut of TFT gate

via

hole in the new process verification experiment

the PVX1 film quality is improved by adjusting the PECVD film formation parameters. The optimum film formation condition is selected to further adjust the dry etch process

and an excellent slope angle is obtained. On the TFT substrate which uses the optimized one-step etching process

the PVX1 slope angle of gate

via

hole is less than 40° and there is no significant step between the PVX1 and the GI layer

and there is no obvious step between the PVX1 and the GI layer. The mass production rate of the DCS caused by the absence of the organic film is reduced to zero. By optimizing the process

the product defect rate is reduced while the process steps are reduced and the production capacity is increased.

关键词

Keywords

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