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1.合肥工业大学 微电子设计研究所, 安徽 合肥 230009
2.深圳清华大学研究院, 广东 深圳 518057
[ "孟宇(1994-), 男, 安徽宿州人, 硕士研究生, 2019年于合肥工业大学获得硕士学位, 主要研究方向为模拟集成电路设计和OLED显示驱动。E-mail:18883285803@139.com" ]
[ "贾晨(1978-), 男, 山西临汾人, 博士, 副研究员, 2009年于清华大学获得博士学位, 主要研究方向包括显示驱动电路芯片设计、电源管理电路和高速串行接口电路等。E-mail:jiachen@tsinghua.edu.cn" ]
收稿日期:2018-10-17,
录用日期:2019-1-22,
纸质出版日期:2019-04
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孟宇, 尹勇生, 宇跃峰, 等. 应用于AMOLED源极驱动的高精度DAC设计[J]. 液晶与显示, 2019,34(4):379-385.
Yu MENG, Yong-sheng YIN, Yue-feng YU, et al. High precision DAC design for AMOLED source drive[J]. Chinese journal of liquid crystals and displays, 2019, 34(4): 379-385.
孟宇, 尹勇生, 宇跃峰, 等. 应用于AMOLED源极驱动的高精度DAC设计[J]. 液晶与显示, 2019,34(4):379-385. DOI: 10.3788/YJYXS20193404.0379.
Yu MENG, Yong-sheng YIN, Yue-feng YU, et al. High precision DAC design for AMOLED source drive[J]. Chinese journal of liquid crystals and displays, 2019, 34(4): 379-385. DOI: 10.3788/YJYXS20193404.0379.
针对OLED显示面板更高分辨率、更高精度的需求,本文提出了一种应用于高分辨率AMOLED源极驱动的高精度10 bit DAC结构。设计的DAC由6 bit的GAMMA校正电阻串DAC及4 bit的基于尾电流源插值的输出缓冲器级联构成,达到高精度的同时占用较小的芯片面积。为进一步提高AMOLED驱动的灰阶电压精度,增加了一个DAC斜率可编程单元对线性DAC输出曲线进行进一步调节,以更好地拟合AMOLED显示屏所需的灰阶-电压曲线,此外,输出缓冲器采用尾电流源插值的方法来实现高精度的第二级DAC。在UMC 80 nm CMOS工艺下,仿真结果表明设计的DAC的最大INL和DNL分别为0.47 LSB、0.24 LSB。在10 kΩ电阻及30 pF电容负载下,DAC电压从最低灰阶到最高灰阶的建立时间为3.38
μ
s。驱动电路可以快速、精确地将图像数据转换为建立在像素电路上的电压,满足分辨率为1080×2 160驱动芯片的应用需求。
The paper proposes a high-precision 10-bit DAC structure for high resolution AMOLED source drive for higher resolution and higher precision of OLED display panel.The DAC consists of a 6-bit GAMMA correction resistor-string DAC and a 4-bit output buffer based on interpolation of the tail current
achieve high precision while occupying a small chip area.In order to further improve the gray-voltage precision of AMOLED drive
a DAC slope programmable unit is added to further adjust the linear DAC output curve to better fit the gray-voltage curve required by AMOLED display. In addition
the output buffer adopts the interpolation method of tail current to realize the high-precision sub-DAC. The simulation results under UMC 80 nm CMOS process show that the proposed DAC with INL and DNL of 0.47 LSB and 0.24 LSB
respectively. The settling time of DAC voltage from the lowest gray-scale to the highest gray-scale is 3.38
μ
s with a 10 kΩ resistance and 30 pF capacitance load. The drive circuit can quickly and accurately convert the image data to the voltage established on the pixel circuit
it can satisfy the application requirements of drive chip with resolution of 1 080×2 160.
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LU C W, HSIAO C M, LIN Y S, et al. A 10-Bit DAC with 1.6-bit interpolation cells for compact LCD column driver ICs[J]. Journal of Display Technology, 2013, 9(3):176-183.
陈宏, 曾龄宇, 胡乔, 等.一种用于轨到轨运算放大器的新型频率补偿结构[J].微电子学, 2011, 41(1):15-18.
CHEN H, ZENG L Y, HU Q, et al. A novel frequency compensation structure for rail-to-rail operational amplifiers[J]. Microelectronics, 2011, 41(1):15-18. (in Chinese)
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