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香港科技大学 先进显示与光电子技术国家重点实验室, 香港
[ "张猛(1985-), 男, 博士, 副研究员, 主要从事薄膜晶体管方面的研究。E-mail:zhangmeng@connenct.ust.hk" ]
郭海成(1951-), 男, IEEE院士, 美国光学学会院士, 国际信息显示学会院士, 亚太材料科学院院士。现任香港科技大学先进显示与光电子技术国家重点实验室主任。E-mail:eekwok@ust.hk
收稿日期:2016-09-19,
录用日期:2016-11-10,
纸质出版日期:2017-02-05
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张猛, 夏之荷, 周玮, 等. 搭桥晶粒多晶硅薄膜晶体管栅交流电应力下的退化行为与退化机制研究[J]. 液晶与显示, 2017,32(2):91-96.
Meng ZHANG, Zhi-he XIA, Wei ZHOU, et al. Degradation behavior and degradation mechanism of bridged-grain polycrystalline silicon thin film transistors under AC gate bias stress[J]. Chinese journal of liquid crystals and displays, 2017, 32(2): 91-96.
张猛, 夏之荷, 周玮, 等. 搭桥晶粒多晶硅薄膜晶体管栅交流电应力下的退化行为与退化机制研究[J]. 液晶与显示, 2017,32(2):91-96. DOI: 10.3788/YJYXS20173202.0091.
Meng ZHANG, Zhi-he XIA, Wei ZHOU, et al. Degradation behavior and degradation mechanism of bridged-grain polycrystalline silicon thin film transistors under AC gate bias stress[J]. Chinese journal of liquid crystals and displays, 2017, 32(2): 91-96. DOI: 10.3788/YJYXS20173202.0091.
本文主要研究了搭桥晶粒(BG)多晶硅薄膜晶体管(TFT)在栅交流电应力下的退化行为和退化机制。在栅交流应力下,动态热载流子效应主导了器件的退化。器件退化只与栅脉冲下降沿有关。越快的下降沿带来越大的动态热载流子退化。比起普通多晶硅TFT,BG多晶硅TFT的热载流子退化大幅度减弱。通过选择性的掺杂注入BG线,沟道中形成的PN结在反向偏置时可以有效分担栅交流电应力带来的电压差,从而减弱动态热载子退化。辅以瞬态模拟结果,栅交流电应力下的退化机制被阐明。所有的测试结果都表明这种高性能高可靠性的BG多晶硅TFT在片上系统应用中具有很大的应用前景。
Degradation behavior and degradation mechanism of bridged-grain (BG) polycrystalline silicon thin film transistors (TFTs) under AC gate bias stress are studied and investigated. It is found that dynamic hot carrier (HC) effect dominates the device degradation. The degradation is only related to gate pulse falling time (
t
f
). Faster
t
f
brings larger dynamic HC degradation. Compared with normal poly-Si TFTs
the dynamic HC degradation of BG poly-Si TFTs under the same stress is greatly reduced. By selectively doping the active channel
the multiple PN junctions inherent can effectively share the voltage drop
resulting in better dynamic HC reliability. Based on transient simulations
the related degradation mechanism is clarified. All test results indicate that such high-performance and highly reliable BG poly-Si TFTs have great potential in system-on-panel applications.
ZHANG M, ZHOU W, CHEN R S, et al. A simple method to grow thermal SiO 2 interlayer for high-performance SPC poly-Si TFTs using Al 2 O 3 gate dielectric[J]. IEEE Electron Device Lett., 2014, 35(5):548-550.
ZHAO S Y, MENG Z G, ZHOU W, et al. Bridged-grain polycrystalline silicon thin-film transistors[J]. IEEE Trans. Electron Devices, 2013, 60(6):1965-1970.
ZHOU W, MENG Z G, ZHAO S Y, et al. Bridged-grain solid-phase-crystallized polycrystalline-silicon thin-film transistors[J]. IEEE Electron Device Lett., 2012, 33(10):1414-1416.
ZHANG M, ZHOU W, CHEN R S, et al. High-performance polycrystalline silicon thin-film transistors integrating sputtered aluminum-oxide gate dielectric with bridged-grain active channel[J]. Semicond. Sci. Technol., 2013, 28(11):115003.
ZHOU W, ZHAO S Y, CHEN R S, et al. Study of the characteristics of solid phase crystallized bridged-grain poly-Si TFTs[J]. IEEE Trans. Electron Devices, 2014, 61(5):1410-1416.
ZHOU W, HO J Y L, ZHAO S Y, et al. Fabrication of bridged-grain polycrystalline silicon thin film transistors by nanoimprint lithography[J]. Thin Solid Films, 2013, 534:636-639.
ZHANG M, ZHOU W, CHEN R S, et al. Characterization of DC-stress-induced degradation in bridged-grain polycrystalline silicon thin-film transistors[J]. IEEE Trans. Electron Devices, 2014, 61(9):3206-3212.
张猛, 夏之荷, 周玮, 等.搭桥晶粒多晶硅薄膜晶体管直流电应力下的退化行为与退化机制研究[J].液晶与显示, 2015, 30(2):187-193. ZHANG M, XIA Z H, ZHOU W, et al. Degradation behaviors and degradation mechanisms of bridged-grain polycrystalline silicon thin film transistors under DC bias stresses[J]. Chin. J. Liq. Cryst. Disp., 2015, 30(2):187-193. (in Chinese)
ZHANG M, WONG M X, LU X W, et al. Analysis of degradation mechanisms in low-temperature polycrystalline silicon thin-film transistors under dynamic drain stress[J]. IEEE Trans. Electron Devices, 2012, 59(6):1730-1737.
CHANG K M, CHUNG Y H, LIN G M, et al. Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress[J]. IEEE Electron Device Lett., 2001, 22(10):475-477.
ZHANG M, XIA Z H, ZHOU W, et al. Significant reduction of dynamic negative bias stress-induced degradation in bridged-grain poly-Si TFTs[J]. IEEE Electron Device Lett., 2015, 36(2):141-143.
TAI Y H, HUANG S C, CHEN C K. Analysis of poly-Si TFT degradation under gate pulse stress using the slicing model[J]. IEEE Electron Device Lett., 2006, 27(12):981-983.
LIU P T, LU H Y, CHEN Y C, et al. Degradation of laser-crystallized laterally grown poly-Si TFT under dynamic stress[J]. IEEE Electron Device Lett., 2007, 28(5):401-403.
URAOKA Y, HATAYAMA T, FUYUKI T, et al. Reliability of low temperature poly-silicon TFTs under inverter operation[J]. IEEE Trans. Electron Devices, 2001, 48(10):2370-2374.
MOON K C, LEE J H, HAN M K. The study of hot-carrier stress on poly-Si TFT employing C-V measurement[J]. IEEE Trans. Electron Devices, 2005, 52(4):512-517.
XUE M, WANG M X, ZHU Z, et al. Degradation behaviors of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors under DC bias stresses[J]. IEEE Trans. Electron Devices, 2007, 54(2):225-232.
SIMMONS J G, TAYLOR G W. Nonequilibrium steady-state statistics and associated effects for insulators and semiconductors containing an arbitrary distribution of traps[J]. Phys. Rev. B, 1971, 4(2):502-511.
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