基于FPGA的CameraLink输出编码设计

刘彪; 王建立; 吕耀文; 曹景太

doi:10.3788/YJYXS20153002.0269

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基于FPGA的CameraLink输出编码设计

器件驱动与控制 | 更新时间：2020-08-12

- 基于FPGA的CameraLink输出编码设计
- Design of camera link output encoding based on FPGA
- 液晶与显示 2015年30卷第2期页码：269-274
- 作者机构：
  
  1. 中国科学院大学北京,中国,100049
  2. 中国科学院长春光学精密机械与物理研究所,吉林长春,130033
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20153002.0269
  中图分类号： TP391
- 收稿日期：2014-07-15，
  
  修回日期：2014-07-31，
  
  纸质出版日期：2015-04-05
- 稿件说明：
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刘彪, 王建立, 吕耀文, 曹景太. 基于FPGA的CameraLink输出编码设计[J]. 液晶与显示, 2015,30(2): 269-274

LIU Biao, WANG Jian-li, LV Yao-wen, CAO Jing-tai. Design of camera link output encoding based on FPGA[J]. , 2015,30(2): 269-274
刘彪, 王建立, 吕耀文, 曹景太. 基于FPGA的CameraLink输出编码设计[J]. 液晶与显示, 2015,30(2): 269-274 DOI： 10.3788/YJYXS20153002.0269.

LIU Biao, WANG Jian-li, LV Yao-wen, CAO Jing-tai. Design of camera link output encoding based on FPGA[J]. , 2015,30(2): 269-274 DOI： 10.3788/YJYXS20153002.0269.

摘要

为了Camera Link摄像机的小型化和集成化

设计并实现了基于FPGA的Camera Link接口的编码输出功能。输出编码分为3个步骤:首先

完成图像像素数据到Camera Link PORT的映射;其次

根据DS90CR287的数据编码要求对PORT数据和同步时钟信号进行编码;最后

通过FIFO和并串转换功能模块完成图像数据和时钟编码信号的LVDS信号输出。使用ModelSim软件

对像素时钟为40 MHz的BASE模式进行了仿真

同时在实物实验中

完成了像素时钟为40 MHz的FULL模式的实验

通过以上两方面实验验证了设计的Camera Link输出编码方案的正确性和可行性。提出的编码方案稳定可靠

可以应用于不同模式下的Camera Link编码输出

具有很高的灵活性和应用价值。

Abstract

In order to miniaturize and integrate Camera Link camera

an output-encoding function based on Camera Link interface was designed and implemented. The implementation is divided into three steps: firstly

mapping image pixel data to the Camera Link PORT; secondly

encoding the PORT data and synchronous clock signal according to the data coding requirements of DS90CR287; finally

completing the LVDS output which contains the image data and clock signal through FIFO and parallel-to-serial conversion module. The BASE model that the pixel clock is 40 MHz was emulated using ModelSim

at the same time

the FULL model that the pixel clock is 40 MHz was experimented. The experimental results demonstrate the correctness and feasibility of the Camera Link output encoding scheme. The proposed coding scheme is stable and reliable

it can be used in different modes

with high flexibility and practicability.

关键词

Keywords

references

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