过孔刻蚀工艺优化对过孔尺寸减小的研究

李田生; 陈旭; 谢振宇; 徐少颖; 闵泰烨; 张学智

doi:10.3788/YJYXS20142905.0674

您当前的位置：

首页 >

文章列表页 >

过孔刻蚀工艺优化对过孔尺寸减小的研究

材料物理和化学 | 更新时间：2020-08-12

- 过孔刻蚀工艺优化对过孔尺寸减小的研究
- Improvement research of via hole minimized by via hole etch conditions
- 液晶与显示 2014年29卷第5期页码：674-680
- 作者机构：
  
  北京京东方光电科技有限公司, 北京 100176
- 作者简介：
- 基金信息：
  
  via hole minimize（No.10S_VHM）()
- DOI：10.3788/YJYXS20142905.0674
  中图分类号： TN141.9
- 收稿日期：2014-01-01，
  
  修回日期：2014-02-15，
  
  网络出版日期：2013-04-16，
  
  纸质出版日期：2014-10-05
- 稿件说明：
移动端阅览
李田生, 陈旭, 谢振宇, 徐少颖, 闵泰烨, 张学智. 过孔刻蚀工艺优化对过孔尺寸减小的研究[J]. 液晶与显示, 2014,29(5): 674-680

LI Tian-sheng, CHEN Xu, XIE Zhen-yu, XU Shao-ying, MIN Tai-ye, ZHANG Xue-zhi. Improvement research of via hole minimized by via hole etch conditions[J]. , 2014,29(5): 674-680
李田生, 陈旭, 谢振宇, 徐少颖, 闵泰烨, 张学智. 过孔刻蚀工艺优化对过孔尺寸减小的研究[J]. 液晶与显示, 2014,29(5): 674-680 DOI： 10.3788/YJYXS20142905.0674.

LI Tian-sheng, CHEN Xu, XIE Zhen-yu, XU Shao-ying, MIN Tai-ye, ZHANG Xue-zhi. Improvement research of via hole minimized by via hole etch conditions[J]. , 2014,29(5): 674-680 DOI： 10.3788/YJYXS20142905.0674.

摘要

为了适应TFT-LCD小型化与窄边框化以及在面板布线精细化的趋势，提高工艺设计富裕量以及增加面板的实际利用率，之前做过钝化层沉积工艺优化来减小液晶面板阵列工艺中连接像素电极与漏极的过孔尺寸的研究。本文在此基础上进行过孔刻蚀工艺的优化，从而最终达到进一步减小过孔尺寸实现TFT-LCD小型化与窄边框化的趋势。通过设计实验考察了影响过孔大小刻蚀主要影响因素（功率、压强、气体比率、刻蚀速率选择比）。实验结果表明，在薄膜沉积优化的基础上可使过孔的尺寸再降低10%~20%。对其进行了良率检测与工艺稳定性评价，最终获得了过孔尺寸减小的方案，并成功导入到产品生产中，从而提高了产品品质。

Abstract

In order to follow with the trend of miniaturization narrow frame and fine wiring structure

the TFT-LCD tends to develop for large margin of design and high real substrate utilization rate. The passivation layer deposit parameters were changed to decrease the size of via hole which connected the pixel electrode and drain electrode were studied on the previous articles. In this paper

based on the previous data

via hole etch process optimization were studied

and finally to get further improvement in hole size to meet the trend of miniaturization and narrow frame on TFT-LCD panel.The main parameters (power

pressure

gas ratio

etch rate ratio) to minimize via hole by etching process through the experiments design were studied. A solution to further minimize the via hole size about 10%~20% which refered to previous study was found. The array yield test and process stability test were evaluated.Finally

one better solution to minimize via hole size was obtained and applied into mass production.Therefore

the products quality was improved also.

关键词

Keywords

references

友达新世代移动显示器技术2011日本国际平面显示器展中首度亮相[J]. 现代显示, 2011(11):38. The new generation mobile display technology of AUO debut in 2011 Japan's international exhibition flat panel display[J].Advanced Display,2011(11):38. (in Chinese)[2] 友达于日本国际平面显示器展展出多元应用创新显示技术[J]. 现代显示, 2011(11):39-40. Multiple display technology application innovation of AUO show in Japan's international exhibition flat panel display[J].Advanced Display,2011(11):39-40. (in Chinese)[3] 董杰,金相起,朴范求,等. a-Si TFT LCD过孔尺寸的缩减[J]. 液晶与显示, 2008,23(6):688-691. Dong J, Jin X Q, Piao F Q,et al.Via hole reduction for a-Si TFT-LCD[J].Chinese Journal of Liquid Crystals and Displays,2008,23(6):688-691.(in Chinese)[4] 李田生,谢振宇,张文余,等. 钝化层沉积工艺对过孔尺寸减小的研究[J]. 液晶与显示, 2012,27(4):493-498. Li T S, Xie Z Y, Zhang W Y,et al.Improvement research of VIA hole minimize by passivation layer deposit conditions[J].Chinese Journal of Liquid Crystals and Displays,2012,27(4):493-498. (in Chinese)[5] 王晓光,朱晓明,尹延昭,等. 等离子体刻蚀工艺的优化研究[J]. 中国新技术新产品, 2010 (14):22. Wang X G, Zhu X M, Yin Y Z,et al.Improvement research of plasma etch[J].Chinese China New Technologies and Products,2010(14):22. (in Chinese)[6] 王刚,李威,李平,等. 基于CF4/Ar高密度感应耦合等离子体的BZN薄膜的刻蚀工艺研究[J]. 材料导报, 2012,26(18):1-3,13. Wang G, Li W. Li P,et al.High density inductively coupled plasma etching of BZN thin film by CF4/Ar[J].Material Technology,2012,26(18):1-3,13. (in Chinese)[7] 赵瑜,江洵,李成垚,等. 二氧化硅纳米颗粒的反应离子刻蚀及其在硅纳米针尖制备中的应用[J]. 纳米技术与精密工程, 2009,7(6):515-518. Zhao Y, Jiang X, Li C G,et al.RIE of SiO2 Nanoparticles and its application in preparation of silicon nanopillar array[J].Nanotechnology and Precision Engineering,2009,7(6):515-518.(in Chinese)[8] 赵飞,党元兰. 金薄膜的反应离子刻蚀工艺研究[J]. 电子工艺技术, 2012,33(1):53-56. Zhao F, Dang Y L. Study on reactive ion etching technology of Au thin film[J].Electronics Process Technology,2012,33(1):53-56.(in Chinese)

浏览量

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

钝化层沉积工艺对过孔尺寸减小的研究

高分辨率主动驱动型氮化镓基Micro-LED芯片的制备

TFT-LCD制造工艺中金属或金属复合膜层坡度角的研究

垂直线不良分析与改善

TFT制程中高厚度ITO残留因素的研究