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暨南大学 信息科学技术学院 电子工程系,广东 广州 510630
[ "作者简介: 邓婉玲(1980-),女,广东佛山人,博士,讲师,主要研究方向为器件建模与仿真验证工具的研究与开发。" ]
收稿日期:2010-08-20,
修回日期:2010-09-07,
网络出版日期:2011-04-06,
纸质出版日期:2011-04-06
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邓婉玲. 多晶硅薄膜晶体管的栅电容模型[J]. 液晶与显示, 2011,26(2): 178-182
DENG Wan-ling. Gate Capacitance Model of Polysilicon Thin Film Transistors[J]. , 2011,26(2): 178-182
邓婉玲. 多晶硅薄膜晶体管的栅电容模型[J]. 液晶与显示, 2011,26(2): 178-182 DOI: 10.3788/YJYXS20112602.0178.
DENG Wan-ling. Gate Capacitance Model of Polysilicon Thin Film Transistors[J]. , 2011,26(2): 178-182 DOI: 10.3788/YJYXS20112602.0178.
多晶硅薄膜晶体管具有独特的栅电容特性
即泄漏区中栅源电容的反常增大和饱和区中栅漏电容由于kink效应的增大。基于Meyer模型
考虑了泄漏产生效应和kink效应
对多晶硅薄膜晶体管的栅漏电容和栅源电容特性进行了建模研究。对实验数据进行拟合发现
提出的模型与实验数据符合得较好
能准确地预测多晶硅薄膜晶体管的栅电容特性。
Polysilicon thin film transistors have unique gate capacitance features
that is
the anomalous increase of gate-to-source capacitance in leakage region and gate-to-drain capacitance in kink region. Based on the Meyer model
taking leakage generation effect and kink effect into account
gate-to-source capacitance and gate-to-drain capacitance characteristics are modeled. The good agreement between simulated model results and experimental data confirms the accuracy and efficiency of this model.
Meyer J. MOS models and circuit simulation [J]. RCA Review, 1971, 32:42-63.[2] Jacunski M D. Characterization and modeling of short-channel polysilicon thin-film transistors . Charlottesville: Univ. of Virginia, 1997.[3] Bindra S, Haldar S, Gupta R S. Gate capacitance characteristics of a poly-Si thin film transistor [J]. Solid-State Electron., 2004, 48(5):675-681.[4] Chen S S, Shone F C, Kuo J B. A closed-form inversion-type polysilicon thin-film transistor dc/ac model conside-ring the kink effect [J]. J. Appl. Phys., 1995, 77(4):1776-1784.[5] Yang G Y, Hur S H, Han C H. A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation [J]. IEEE Trans. Electron Devices, 1999, 46(1):165-172.[6] Chung S S, Chen D C, Cheng C T, et al. A physically-based built-in spice poly-Si TFT model for circuit simulation and reliability evaluation //Proceedings of the 1996 IEEE International Electron Devices Meeting, Piscataway: IEEE, 1996:139-142.[7] Li C C, Ikeda H, Inoue T, et al. A physical poly-Silicon thin film transistors model for circuit simulations // Proceedings of the 1993 IEEE International Electron Devices Meeting, Piscataway: IEEE, 1993: 497-500.[8] Martin R A, Hack M, Shaw J G, et al. Intrinsic capacitance of amorphous silicon and polysilicon thin film transistors //IEEE International Electron Devices Meeting, Piscataway: IEEE, 1989:361-364.[9] Cadence Design Systems, Inc. Cadence Circuit Components and Device Models Manual [M]. San Jose, USA:Cadence Design Systems, Inc., 2005:1365-1400.
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