铜工艺阵列基板上数据线和公共电极不可见的短路原因分析及改善

林忱; 冯玉春; 陈曦; 汤桂泉; 李鑫; 周贺; 刘文瑞; 贠向南

doi:10.37188/YJYXS20203510.1036

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铜工艺阵列基板上数据线和公共电极不可见的短路原因分析及改善

器件驱动与控制 | 更新时间：2020-09-28

- 铜工艺阵列基板上数据线和公共电极不可见的短路原因分析及改善
- Research and improvement of data line and common line invisible short in copper process array substrate
- 液晶与显示 2020年35卷第10期页码：1036-1043
- 作者机构：
  
  福州京东方光电科技有限公司, 福建福州 350300
- 作者简介：
  
  [ "林忱(1989-), 男, 福建福州人, 硕士, 工程师, 2015年于东南大学获得硕士学位, 主要从事TFT-LCD工艺技术的研究。E-mail:linchen_1102@126.com" ]
- 基金信息：
- DOI：10.37188/YJYXS20203510.1036
  中图分类号： TN873.93
- 收稿日期：2020-03-31，
  
  修回日期：2020-04-24，
  
  录用日期：2020-4-24，
  
  纸质出版日期：2020-10-05
- 稿件说明：
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林忱, 冯玉春, 陈曦, 等. 铜工艺阵列基板上数据线和公共电极不可见的短路原因分析及改善[J]. 液晶与显示, 2020,35(10):1036-1043.

Chen LIN, Yu-chun FENG, Xi CHEN, et al. Research and improvement of data line and common line invisible short in copper process array substrate[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1036-1043.
林忱, 冯玉春, 陈曦, 等. 铜工艺阵列基板上数据线和公共电极不可见的短路原因分析及改善[J]. 液晶与显示, 2020,35(10):1036-1043. DOI： 10.37188/YJYXS20203510.1036.

Chen LIN, Yu-chun FENG, Xi CHEN, et al. Research and improvement of data line and common line invisible short in copper process array substrate[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1036-1043. DOI： 10.37188/YJYXS20203510.1036.

摘要

本文针对铜工艺TFT-LCD制作过程中遇到的不可见的数据信号线和公共电极信号线短路（DCS），提出切割实验方案，精确定位不可见类型的DCS异常的实际位置。基于数据和失效模式分析结果，设计不同灰化工艺时间膜层形貌观察实验，探究发生机理。本文产出的异常发生机理是灰化过程中反应气体SF

残留在“屋檐状”光刻胶下方对公共电极Cu金属造成腐蚀，在产线湿度高的情况下易加剧腐蚀，腐蚀产物向上生长，后续栅极绝缘层/活性层镀膜无法完全覆盖住腐蚀产物，造成源、漏（Source

Drain，SD）层镀膜后数据线与腐蚀产物相连接，最终形成TFT基板膜层正面不可见的DCS异常。依据以上调查结果进行灰化工艺SF

气体用量、产线相对湿度（RH）、灰化工序至2

栅极湿刻工序等待时间和设计相关的改善验证，最终通过量产导入灰化工艺SF

气体用量降低、产线相对湿度（RH）降低、缩短灰化工序至2

栅极湿刻工序等待时间和优化异常发生区域开槽设计以增大间距

等改善措施，大幅减少了不可见类型的DCS异常。

Abstract

Contrapose data line and common line invisible short(DCS Invisible) in production of copper process array substrate

a new method based on cutting for locating the position of DCS Invisible is presented. Based on the result of data and failure analysis

an observation experiment of layer section with different ashing process time is designed to explore the mechanism. In ashing process

reaction gas SF

below the photoresist which looks like the shape of roof will corrode copper metal of common line. Under the condition of high humidity

the corrosion will be aggravated. Corrosion products grow up and can't be covered by thin film of GI/Active. After thin film process of SD(Source

Drain)

the data line will connect with corrosion products and finally cause DCS which is invisible on the front side of array substrate. Based on the research

the experiment of reaction gas consumption of SF

in ashing process

relative humidity

waiting time from Ashing to 2

Gate Wet Etch and design improvement is proceeded. Finally

DCS Invisible is solved by reducing reaction gas consumption of SF

decreasing relative humidity

controlling waiting time from Ashing to 2

Gate Wet Etch and insuring space

of slotting design larger.

关键词

Keywords

references

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