栅极坡度角对TFT器件制程的影响

刘丹; 刘毅; 黄中浩; 高坤坤; 吴旭; 田茂坤; 王恺; 张超; 王瑞; 闵泰烨; 冯家海; 方亮

doi:10.37188/YJYXS20203510.1026

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栅极坡度角对TFT器件制程的影响

器件物理及器件制备技术 | 更新时间：2020-09-28

- 栅极坡度角对TFT器件制程的影响
- Influence of gate profile on TFT manufacturing process
- 液晶与显示 2020年35卷第10期页码：1026-1035
- 作者机构：
  
  1.重庆京东方光电科技有限公司, 重庆 400700
  2.重庆大学物理学院, 重庆 400044
  3.中国科学院重庆绿色智能技术研究院, 重庆 400714
- 作者简介：
  
  [ "刘丹(1988-), 男, 重庆忠县人, 博士研究生, 高级工程师, 2014年于四川大学获得硕士学位, PMP、工信部可靠性工程师、数据分析师(CPDA, 国际TRIZ协会二级认证), 主要从事TFT-LCD工艺研究。E-mail:liudan_cq@boe.com.cn" ]
  [ "刘毅(1983-), 男, 江西九江人, 硕士, 博士研究生, 资深高级工程师, 2015年于中国人民大学获得硕士学位, 主要从事TFT-LCD生产制造工作。E-mail:liuyi@boe.com.cn" ]
- 基金信息：
- DOI：10.37188/YJYXS20203510.1026
  中图分类号： TN304;TN141.9
- 收稿日期：2020-03-20，
  
  修回日期：2020-05-14，
  
  录用日期：2020-5-14，
  
  纸质出版日期：2020-10-05
- 稿件说明：
移动端阅览
刘丹, 刘毅, 黄中浩, 等. 栅极坡度角对TFT器件制程的影响[J]. 液晶与显示, 2020,35(10):1026-1035.

Dan LIU, Yi LIU, Zhong-hao HUANG, et al. Influence of gate profile on TFT manufacturing process[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1026-1035.
刘丹, 刘毅, 黄中浩, 等. 栅极坡度角对TFT器件制程的影响[J]. 液晶与显示, 2020,35(10):1026-1035. DOI： 10.37188/YJYXS20203510.1026.

Dan LIU, Yi LIU, Zhong-hao HUANG, et al. Influence of gate profile on TFT manufacturing process[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1026-1035. DOI： 10.37188/YJYXS20203510.1026.

摘要

薄膜晶体管（Thin film transistor，TFT）的栅极在截面方向上是一个台阶，栅极绝缘层（Gate Insulator，GI）和源漏极（Source和Data电极，SD电极）依次覆盖于台阶之上，覆盖程度以台阶覆盖率（台阶处GI层水平厚度与竖直厚度的比值）进行衡量。本文结合重庆京东方的HADS产品工艺制程，探究了栅极厚度、坡度角对GI层的台阶覆盖率的影响。同时，在覆盖率的基础上研究了台阶处和非台阶处的SD膜层刻蚀程度差异。结合量产中的不良，分析栅极坡度角、覆盖率、栅极腐蚀等相关不良的关系，并提出相应的良率提升措施。实验结果表明：坡度角是影响GI覆盖率的关键因素，且栅极坡度角与GI覆盖率呈负线性关系。当栅极厚度在280~500 nm范围变化时，栅极坡度角每增加10°，GI层台阶覆盖率下降约20%。SD膜层覆盖在台阶上，因台阶的存在造成此处的SD层减薄，最终导致该处的SD膜层刻蚀程度加大。如果栅极坡度角偏大，会导致台阶处GI层减薄或者产生微裂纹，工艺制程中的腐蚀介质会透过减薄的GI层进而腐蚀栅极；此外，偏大的栅极坡度角会导致台阶处的SD电极有断线的风险。通过刻蚀液种类变更、刻蚀液成分微调、刻蚀工艺的优化可以降低栅极坡度角，规避上述良率风险。此外，对于栅极腐蚀型不良，也可以通过调整GI层的成膜参数来提升覆盖率。对于SD电极断线风险，可尝试增加光刻胶粘附力、台阶处SD线加宽等措施规避风险。

Abstract

The gate electrode of thin film transistor(TFT) is a step in cross section

it is covered by gate insulator(GI)

source and data electrode(SD electrode) in sequence

and the degree of coverage is measured by the step coverage

which is the ratio of the horizontal thickness to the vertical thickness of GI layer at the step. In this paper

combining the manufacturing process of HADS product in Chongqing BOE company

the influence of gate thickness and profile on the GI layer step coverage is studied. Then

the difference of SD etching degree between step and non-step is explored based on step coverage. After that

the relationship between gate profile

step coverage

Cu corrosion and other defects are analyzed based on defect information in mass production. At last

the corresponding yield up measures are proposed. The experimental results show that the tate profile is a key factor affecting step coverage

and gate profile has a negative linear relationship with GI coverage. When the gate thickness varies from 280 nm to 500 nm

the GI coverage decreases by 20% for every 10° increase in the gate profile. SD layer covers the step

and will be thinned at this place

which leads to an increase in the degree of SD etching. If the gate profile is large

the GI layer at the step will be thinned or generates micro-cracks

the corrosive medium in manufacturing process will pass through the thinned GI layer or crack to react with gate electrode to form corrosion. Whats more

a larger gate profile will cause SD line to be open at the step. A gentle gate profile can be obtained to avoid the above yield risk by changing etchant

adjusting etchant composition

optimizing etch process. In addition

it is a useful method to adjust GI deposition parameter to improve GI coverage to avoid gate corrosion; and the solution containing improving photo-resist adhesion

widening the SD line at the step can be tried to avoid SD line open.

关键词

Keywords

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