图像处理算法IP核的异构验证框架

赵陆; 文建平; 莫为; 陈仕睿; 李项河

doi:10.37188/CJLCD.2020-0322

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图像处理算法IP核的异构验证框架

图像处理 | 更新时间：2021-07-13

- 图像处理算法IP核的异构验证框架
- Heterogeneous verification framework of IP core for image processing algorithm
- 液晶与显示 2021年36卷第7期页码：1042-1050
- 作者机构：
  
  1.西安科技大学机械工程学院, 陕西西安 710054
  2.陕西科技控股集团有限责任公司, 陕西西安 710000
  3.西安西微智能科技有限公司, 陕西西安 710000
- 作者简介：
  
  [ "赵陆(1996-), 男, 河北石家庄人, 硕士研究生, 2018年于河北科技大学获得学士学位, 主要从事图像处理算法在FPGA和SoC中的应用研究。E-mail:z2595426920@163.com" ]
  [ "文建平(1977-), 男, 陕西西安人, 博士, 副教授, 2010年于西安交通大学获得博士学位, 主要从事新能源汽车与机器人方面的研究。E-mail: zhongyang224@126.com" ]
- 基金信息：
  
  基于无线供电技术的机器人智能巡检系统(2016KTZDGY4-05)
- DOI：10.37188/CJLCD.2020-0322
  中图分类号： TP391;TN492
- 收稿日期：2020-11-30，
  
  修回日期：2020-12-16，
  
  纸质出版日期：2021-07
- 稿件说明：
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赵陆, 文建平, 莫为, 等. 图像处理算法IP核的异构验证框架[J]. 液晶与显示, 2021,36(7):1042-1050.

Lu ZHAO, Jian-ping WEN, Wei MO, et al. Heterogeneous verification framework of IP core for image processing algorithm[J]. Chinese journal of liquid crystals and displays, 2021, 36(7): 1042-1050.
赵陆, 文建平, 莫为, 等. 图像处理算法IP核的异构验证框架[J]. 液晶与显示, 2021,36(7):1042-1050. DOI： 10.37188/CJLCD.2020-0322.

Lu ZHAO, Jian-ping WEN, Wei MO, et al. Heterogeneous verification framework of IP core for image processing algorithm[J]. Chinese journal of liquid crystals and displays, 2021, 36(7): 1042-1050. DOI： 10.37188/CJLCD.2020-0322.

摘要

图像处理算法IP核的验证是SoC和FPGA在机器视觉领域应用的关键。为了提高验证时效性，本文基于ARM+FPGA异构平台，联合上位机软件，针对图像处理算法IP核设计了一种兼具泛用型、实时性和敏捷性的验证框架。验证框架通过ARM处理器与上位机建立千兆以太网通信，实现测试激励和测试响应的实时传输，使用FPGA以兼容多类型不同分辨率的图像为目的构建数据总线，配置总线和处理模块，并结合部分重配置实现待验证算法IP核的快速迭代。实验结果表明：验证框架对于以8，16，24 bit位深度图像为处理对象和结果的算法IP核具有可重用性，待验证IP核的部署速度相对全局重配置提高了25倍。与现有的FPGA验证技术相比，具有更好的可重用性，更短的验证周期，并且测试激励更具有针对性，待验证IP核的部署更加敏捷快速。

Abstract

The verification of IP core of image processing algorithm is the key of SoC and FPGA application in the field of machine vision. In order to shorten the verification cycle

based on ARM+FPGA heterogeneous platform and combined with software on PC

a verification framework with universal application

real-time performance and agility is designed for IP core of image processing algorithm. The verification framework establishes gigabit ethernet communication with PC through ARM to realize real-time input of test image and video

uses FPGA to build data bus and configuration bus for the purpose of compatibility with multi-type images

and combines partial reconfiguration to realize fast iteration of IP core of the algorithm to be verified. The validation framework is reusable for the algorithm IP core with 8

and 24 bit depth images as processing objects and results

and the deployment speed of the IP cores to be verified is 25 times faster than global reconfiguration. Compared with the existing FPGA verification technology

it has better reusability

shorter verification cycle

more targeted test stimulus

and faster deployment of IP cores to be verified

关键词

Keywords

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