多工作模式的刷新成像系统

李波; 余达; 刘金国; 孔德柱; 梅贵; 陈佳豫; 赵莹

doi:10.37188/CJLCD.2020-0180

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多工作模式的刷新成像系统

图像处理 | 更新时间：2021-07-13

- 多工作模式的刷新成像系统
- Multi-working mode refresh imaging system
- 液晶与显示 2021年36卷第7期页码：1035-1041
- 作者机构：
  
  中国科学院长春光学精密机械与物理研究所, 吉林长春 130033
- 作者简介：
  
  [ "李波(1967-), 男, 吉林长春人, 学士, 实验师, 1993年于长春市委党校获得学士学位, 主要从事空间遥感方面的研究。E-mail:libo@ciomp.ac.cn" ]
  [ "余达(1980-), 男, 四川内江人, 博士, 副研究员, 2012年于中国科学院长春光学精密机械与物理研究所获得博士学位, 主要从事空间光学遥感方面的研究。E-mail: ciompyuda@163.com" ]
- 基金信息：
  
  National Natural Science Foundation of China;吉林省科技发展计划项目
- DOI：10.37188/CJLCD.2020-0180
  中图分类号： TN386.5;P231
- 收稿日期：2020-07-10，
  
  修回日期：2020-09-09，
  
  纸质出版日期：2021-07
- 稿件说明：
移动端阅览
李波, 余达, 刘金国, 等. 多工作模式的刷新成像系统[J]. 液晶与显示, 2021,36(7):1035-1041.

Bo LI, Da YU, Jin-guo LIU, et al. Multi-working mode refresh imaging system[J]. Chinese journal of liquid crystals and displays, 2021, 36(7): 1035-1041.
李波, 余达, 刘金国, 等. 多工作模式的刷新成像系统[J]. 液晶与显示, 2021,36(7):1035-1041. DOI： 10.37188/CJLCD.2020-0180.

Bo LI, Da YU, Jin-guo LIU, et al. Multi-working mode refresh imaging system[J]. Chinese journal of liquid crystals and displays, 2021, 36(7): 1035-1041. DOI： 10.37188/CJLCD.2020-0180.

摘要

为克服在轨单粒子翻转并实现灵活可靠的多工作模式，设计了基于Xilinx现场可编程逻辑器件和上海复旦微刷新芯片的刷新成像系统。使用单组菊花链结构的串行总线进行5组刷新成像单元串口控制，FPGA将接收到的数据内部转换后再对刷新芯片配置或重注。通过刷新使能信号控制刷新芯片是否加电，同时决定FPGA以主并工作方式从PROM加载还是从并方式在刷新芯片的控制下加载。通过控制电平设置，实现加载数据源的选择。在各供电电源完毕后，使用外部的复位信号对刷新芯片进行复位，满足刷新芯片复位后立即启动配置的时序要求。实验结果表明，以波特率625 kbit/s菊花链方式，传输单包204 byte的数据仅需0.377 6 ms，远低于刷新串口所需的2.01 ms，可以进行多组的分时工作。采用少量单端控制信号结合菊花链串行总线的刷新成像系统，多种工作模式稳定可靠，具备设计灵活性和在轨可维护性。

Abstract

In order to overcome the on-orbit single-event flip and realize flexible and reliable multiple working modes

a refresh imaging system based on Xilinx field programmable logic devices and refresh chip of Fudan Microelectronics group company limited is designed. Using a single set of daisy chain structure serial bus to control the serial port of 5 sets of refresh imaging unit

FPGA internally converts the received data and then configures or refills the refresh chip. The refresh enable signal is used to control whether the refresh chip is powered on

and at the same time decides whether the FPGA is loaded from PROM in the master and parallel mode or loaded under the control of the refresh chip in the parallel mode. Through the control level setting

the selection of the loading data source is realized. After each power supply is completed

the external reset signal is used to refresh the chip reset

meets the timing requirements of refreshing the chip to start configuration immediately after reset. The experimental results show that the transmission time of a single packet of 204 byte data is only 0.377 6 ms with the baud rate of 625 kbit/s in daisy chain mode

which is much lower than the 2.01 ms required to refresh the serial port

and multiple groups of time-sharing work can be performed. The refresh imaging system using a small number of single-ended control signals combined with a daisy chain serial bus has a variety of working modes that are stable and reliable

with design flexibility and on-track maintainability.

关键词

Keywords

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