Design of multi channel high-speed serial image data transmission system based on TLK2711

Da YU; Jing-guo LIU; Dong XU; De-zhu KONG; Jia-yu CHEN; Gui MEI; Lei ZHOU

doi:10.3788/YJYXS20173210.0815

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Design of multi channel high-speed serial image data transmission system based on TLK2711

Image Processing | 更新时间：2020-08-12

- Design of multi channel high-speed serial image data transmission system based on TLK2711
- Chinese Journal of Liquid Crystals and Displays Vol. 32, Issue 10, Pages: 815-821(2017)
- 作者机构：
  
  中国科学院长春光学精密机械与物理研究所, 吉林长春 130033
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20173210.0815
  CLC： TP394.1;TH691.9
- Received：11 March 2017，
  
  Accepted：24 June 2017，
  
  Published：05 October 2017
- 稿件说明：
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Da YU, Jing-guo LIU, Dong XU, et al. Design of multi channel high-speed serial image data transmission system based on TLK2711[J]. Chinese journal of liquid crystals and displays, 2017, 32(10): 815-821.
DOI：

Da YU, Jing-guo LIU, Dong XU, et al. Design of multi channel high-speed serial image data transmission system based on TLK2711[J]. Chinese journal of liquid crystals and displays, 2017, 32(10): 815-821. DOI： 10.3788/YJYXS20173210.0815.

摘要

为提高多路高速串行图像数据传输在航天应用中的FPGA IO利用率，同时克服接收到的多路并行恢复数据相对相位不确定性问题，采用时钟分路器同时为多路TLK2711和FPGA提供低抖动时钟。对于串行数据发送，采用FPGA内部的数字时钟管理单元（DCM）对发送数据的相位进行调整，并采用TLK2711的内部环回功能进行发送数据和时钟相位的动态自适应调整。对于串行数据接收，采用高速异步数据缓存将多路相对相位不确定的数据调理为参考相同时钟，最终转换为满足Camera Link接口协议的图像数据。实验结果表明，采用时钟分路器可大大降低时钟抖动，该传输系统工作稳定可靠，最大传输速率可达6.8 Gbit/s。此方法可大大提高FPGA内部的资源利用率，实现多路并行恢复数据的相对确定相位，满足多通道基于TLK2711的高速串行数据的高稳定传输要求。

Abstract

In order to improve the utilization rate of FPGA IO for multi-channel high-speed serial image data transmission in the space application

and to overcome the relative phase uncertainty of the received multi-channel parallel recovery data

we propose a new design of multi-channel high-speed serial image data transmission system based on TLK2711. One new method is using the clock buffer simultaneously to provide low jitter clock for the multi-channel TLK2711 and FPGA. For serial data transmission

the FPGA internal component digital clock management unit (DCM) is used to adjust the phase

the TLK2711 internal loopback function are carried out for the data and clock phase of the dynamic adaptive adjustment. For serial data reception

high-speed asynchronous data cache is used for data conditioning and meets the Camera Link interface protocol ultimately. The output data have the same reference clock

though the input data have uncertain phase relationship. The experimental results show that the clock buffer can reduce clock jitter

the transmission system is stable and reliable

the maximum transmission rate is up to 6.8 Gbit/s. This method can greatly improve the resource utilization rate within the FPGA and realize the relative stable phase of the multi-channel parallel recovery data to meet the high stability transmission requirements of the multi-channel TLK2711based on high-speed serial data.

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