Design of low power analog-to-digital converter for the control circuit of touch screen

Yun-feng HU; Chun-jian DENG; Bin LI

doi:10.3788/YJYXS20173208.0622

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Design of low power analog-to-digital converter for the control circuit of touch screen

Driver and System | 更新时间：2020-08-12

- Design of low power analog-to-digital converter for the control circuit of touch screen
- Chinese Journal of Liquid Crystals and Displays Vol. 32, Issue 8, Pages: 622-627(2017)
- 作者机构：
  
  1.电子科技大学中山学院, 广东中山 528402
  2.电子科技大学计算机科学与工程学院, 四川成都 610054
  3.华南理工大学电子与信息学院, 广东广州 510640
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20173208.0622
  CLC： TP453
- Received：13 February 2017，
  
  Accepted：13 May 2017，
  
  Published：05 August 2017
- 稿件说明：
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Yun-feng HU, Chun-jian DENG, Bin LI. Design of low power analog-to-digital converter for the control circuit of touch screen[J]. Chinese journal of liquid crystals and displays, 2017, 32(8): 622-627.
DOI：

Yun-feng HU, Chun-jian DENG, Bin LI. Design of low power analog-to-digital converter for the control circuit of touch screen[J]. Chinese journal of liquid crystals and displays, 2017, 32(8): 622-627. DOI： 10.3788/YJYXS20173208.0622.

摘要

为了降低触摸屏控制电路的功耗，本文提出了一种低功耗逐次逼近型模数转换器（SAR ADC）。对该SAR ADC所采用的电容阵列数模转换器（DAC）、比较器和逐次逼近寄存器等进行了研究与设计。首先，基于两级并串耦合电容设计电容阵列DAC结构，并设计配套的参考电平转换方案。接着，设计两级全动态比较器，并分析比较器的工作原理。然后，基于动态逻辑设计低功耗低误码逐次逼近寄存器。最后，基于180 nm CMOS工艺，在1 V电源电压，200 kHz采样频率和96.243 kHz输入频率条件下对SAR ADC进行了仿真。仿真结果表明：积分非线性误差（INL）和微分非线性误差（DNL）分别为0.222/-0.203 LSB和0.231/-0.184 LSB，无杂散动态范围（SFDR）为76.56 dB，信噪失真比（SNDR）为61.50 dB，有效位（ENOB）为9.92位，功耗为0.464

W，品质因素（FOM）值为2.4 fJ/Conv.-step。本文设计的低功耗SAR ADC满足触摸屏控制电路应用要求。

Abstract

In order to reduce the power consumption of the touch screen control circuit

a low power successive approximation analog-to-digital converter (SAR ADC) was proposed. The capacitor array digital-to-analog converter (DAC)

comparator and successive approximation register were studied and designed. Firstly

based on two-stage parallel-series capacitor

the capacitor array DAC and reference voltage switching scheme is designed. Next

two-stage fully dynamic comparator is designed and the principle is analyzed. Then

based on the dynamic logic

successive approximation register with low power and low error code is designed. Finally

the ADC was implemented in 180 nm CMOS technology 1 V power supply and simulated at the input frequency

=96.243 kHz and sampling frequency

=200 kHz. The Simulation result indicates that values of Integral Non-Linearity(INL) and Differential Non-Linearity(DNL) are 0.222/-0.203 LSB and 0.231/-0.184 LSB respectively. Spurious Free Dynamic Range(SFDR) is 76.56 dB

Signal to Noise and Distortion Ratio is 61.50 dB

Effective Number of Bits(ENOB) is 9.92 bits. The power dissipation is only about 0.464 μW

figure of merit (FOM) is equal to 2.4 fJ/Conv.-step. In conclusion

the low power SAR ADC proposed in this paper meets the application requirement of touch screen control circuit.

关键词

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references

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