HD-SDI transmission and display system from camera link full interface data

LIANG Guo-long; HE Ding-long; ZHANG Lei; LIU Yan-jun; WANG Bo

doi:10.3788/YJYXS20163104.0421

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HD-SDI transmission and display system from camera link full interface data

Display and Image | 更新时间：2020-08-12

- HD-SDI transmission and display system from camera link full interface data
- Chinese Journal of Liquid Crystals and Displays Vol. 31, Issue 4, Pages: 421-428(2016)
- 作者机构：
  
  中国科学院长春光学精密机械与物理研究所,吉林长春,中国,130033
- 作者简介：
- 基金信息：
  
  Supported by National 863 Plan Military Project of China(No. 2014AA7031082A)
- DOI：10.3788/YJYXS20163104.0421
  CLC： TN919.8
- Received：08 October 2015，
  
  Revised：28 December 2015，
  
  Published：05 April 2016
- 稿件说明：
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梁国龙, 何丁龙, 张磊等. Camera Link Full至HD-SDI接口的高清传输显示系统[J]. 液晶与显示, 2016,31(4): 421-428

LIANG Guo-long, HE Ding-long, ZHANG Lei etc. HD-SDI transmission and display system from camera link full interface data[J]. , 2016,31(4): 421-428
梁国龙, 何丁龙, 张磊等. Camera Link Full至HD-SDI接口的高清传输显示系统[J]. 液晶与显示, 2016,31(4): 421-428 DOI： 10.3788/YJYXS20163104.0421.

LIANG Guo-long, HE Ding-long, ZHANG Lei etc. HD-SDI transmission and display system from camera link full interface data[J]. , 2016,31(4): 421-428 DOI： 10.3788/YJYXS20163104.0421.

摘要

为实现远距离、高可靠性传输

并减小复杂度

对Camera Link Full接口数据的HD-SDI传输显示进行了深入研究。采用FPGA作为核心处理器

考虑相机输出具有多种帧频

采取帧频检测及充分降频策略

并通过3个SRAM进行缓存以实现帧频转换

以满足HD-SDI帧频25Hz的要求。考虑到SRAM数据宽度

采取FIFO行缓存策略将Camera Link Full80输出的10 tap、80 bits图像数据转换成单通道的8 bits图像数据。最后

完成系统设计并进行实验验证。实验结果表明:系统实现了图像数据从50 Hz、100 Hz、500 Hz等多种帧频的Camera Link Full80到25帧HD-SDI接口1080i的格式转换及实时显示

且图像层次丰富

无失真。

Abstract

In order to achieve long distance transmission with high reliability while reducing complexity

HD-SDI transmission and displaying system for video derived from Camera Link Full interface were researched in detail. FPGA was the core processor. Considering the feature of multi frame rates of the camera

frame rate detection and frequency reduction policy were adopted to preprocess the video. The preprocessed data was buffered by use of three SRAMs to complete the conversion of frame rate. The result met the 25 Hz requirement of HD-SDI. Duo to the bus width of SRAM

FIFO line buffer policy was selected to transfer data from Camera Link Full80

which was 80 bits with 10 tap

to data of 8 bits with single channel. At last

the system was designed and verified in experiment. The experimental result shows that video of multi frame rates from Camera Link Full80

which includes 50 Hz

100 Hz

500 Hz

is converted to the form of 1080i for HD-SDI. The video could be displayed in real time without distortion

and image is clear and structured.

关键词

Keywords

references

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