Via hole contact resistance in TFT-LCD

BAI Jin-chao; WANG Yu-tang; GUO Zong-jie; DING Xiang-qiang; YUAN Jian-feng; SHAO Xi-bin

doi:10.3788/YJYXS20153003.0432

您当前的位置：

首页 >

文章列表页 >

Via hole contact resistance in TFT-LCD

Device Physics & Device Technology | 更新时间：2020-08-12

- Via hole contact resistance in TFT-LCD
- Chinese Journal of Liquid Crystals and Displays Vol. 30, Issue 3, Pages: 432-436(2015)
- 作者机构：
  
  北京京东方显示技术有限公司, 北京 100176
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20153003.0432
  CLC： TN141.9
- Received：29 October 2014，
  
  Revised：17 November 2014，
  
  Published：05 June 2015
- 稿件说明：
移动端阅览
白金超, 王玉堂, 郭总杰, 丁向前, 袁剑峰, 邵喜斌. TFT-LCD过孔接触电阻研究[J]. 液晶与显示, 2015,30(3): 432-436

BAI Jin-chao, WANG Yu-tang, GUO Zong-jie, DING Xiang-qiang, YUAN Jian-feng, SHAO Xi-bin. Via hole contact resistance in TFT-LCD[J]. , 2015,30(3): 432-436
白金超, 王玉堂, 郭总杰, 丁向前, 袁剑峰, 邵喜斌. TFT-LCD过孔接触电阻研究[J]. 液晶与显示, 2015,30(3): 432-436 DOI： 10.3788/YJYXS20153003.0432.

BAI Jin-chao, WANG Yu-tang, GUO Zong-jie, DING Xiang-qiang, YUAN Jian-feng, SHAO Xi-bin. Via hole contact resistance in TFT-LCD[J]. , 2015,30(3): 432-436 DOI： 10.3788/YJYXS20153003.0432.

摘要

研究了过孔接触电阻变化规律

并进行机理分析

为优化薄膜晶体管的过孔设计提供依据.首先

运用开尔文四线检测法对不同大小、形状、数量的钼/铝/钼结构的栅极和源/漏层金属与氧化铟锡连接过孔的接触电阻进行测试.然后

通过扫描电子显微镜、能量色散X射线光谱仪和聚焦离子束显微镜对过孔内部形貌进行表征.最后

对过孔接触电阻变化规律进行机理分析.实验结果表明:过孔面积越大

接触电阻越小;过孔面积相同时

长方形过孔的接触电阻小于正方形过孔的接触电阻

多小孔的接触电阻小于单大孔的接触电阻

栅极金属与氧化铟锡的过孔接触电阻小于源/漏层金属与氧化铟锡的过孔接触电阻.为了降低钼/铝/钼与氧化铟锡连接过孔的接触电阻

过孔面积尽可能最大化

采用长方形过孔优于正方形过孔

多小过孔优于单大孔设计

同时优化过孔刻蚀工艺

减少过孔内顶层钼的损失.

Abstract

In order to optimize via hole design of TFT array substrate and reduce via hole contact resistance

the contact resistance of different size

shape

number of Mo/Al/Mo and Indium-Tin Oxide (ITO) connection via holes are tested by Kelvin Four-terminal sensing. Then via hole morphology is characterized by scanning electron microscopy (SEM)

focused ion beam (FIB) and energy dispersive spectroscopy (EDS). Finally

the mechanism of via hole contact resistance test results are analyzed. Experimental results indicate that the bigger via hole area is

the smaller the contact resistance will be

and in the same via hole area

the contact resistance of rectangular via hole is smaller than that of a square via hole

the contact resistance of the multi small holes is smaller than that of the single big via hole

the via hole contact resistance of Gate metal and ITO is smaller than that of SD metal and ITO. For reducing via hole contact resistance

via hole area is maximized. The rectangular via hole is better than that of the square via hole

the multi small holes are better than that of the single big via hole

and via etch process is optimized to reduce top Mo loss.

关键词

Keywords

references

闫方亮,沈世妃,侯智,等. a-Si厚度对TFT开关特性的影响[J]. 现代显示, 2011,12(7):23-25. Yan F L, Shen S F, Hou Z,et al. Effect of a-Silicon thickness on TFT characteristic [J]. Advanced Display,2011, 12(7): 23-25. (in Chinese)[2] Muhammad M H, Nairn M, Zhan Z B. Metal wet etch issues and effects in dual metal gate stack integration [J]. Journal of the Electrochemical Society, 2006, 153(5): 43-46.[3] 张定涛,李文彬,姚立红,等. 大尺寸TFT-LCD ECCP刻蚀工艺低耗整合[J]. 液晶与显示,2014,29(1):6-13. Zhang D T, Li W B, Yao L H,et al. Low consumption combination of large-sized TFT-LCD ECCP etch process [J]. Chinese Journal of Liquid Crystals and Displays, 2014, 29(1): 7-14. (in Chinese)[4] Kwang-ho J, Soo-jung H, Young-chang J. Effect of capping layer on hillock formation in thin Al films [J]. Metals and Materials International, 2008, 14(2): 147-150.[5] 刘翔,陈旭,谢振宇,等. 使用低电阻金属铝制造薄膜晶体管阵列信号电极[J]. 液晶与显示,2009,24(4):533-536. Liu X, Chen X, Xie Z Y, et al. Low resistant metal for thin film transistors [J]. Chinese Journal of Liquid Crystals and Displays, 2009, 24(4): 533 536. (in Chinese)[6] Gruner G. Carbon nanotube films for transparent and plastic electronics [J]. J Mater Chem, 2006, 16: 3533-3539.[7] 刘翔,薛建设,周伟峰,等. 改善沉积氮化硅薄膜对FFS-TFT透明电极ITO影响的研究[J]. 真空科学与技术学报, 2012,32(1):36-38. Liu X, Xue J S, Zhou W F, et al. Study on the effect of improving the deposition of silicon nitride films on ITO [J]. Vacuum Science and Technology, 2012, 32(1): 36-38. (in Chinese)[8] Lewis B G, Paine D C. Applications and processing of transparent conducting oxides [J]. Mrs Bulletin, 2000, 25(8): 22-27.[9] Seo H S, Choi J B, Yun D C, et al. Simple process of Hillock-free Al-gate metallization without ITO/Al contact problems for large-area TFT-LCDs [J]. SID, 1998, 29: 375-378.

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Quantitative calculation and design method for the resistance of via hole connected by ITO

Optimization of via etching process of LTPS TFT interlayer dielectric

Effect of film layer on photoresist ashing

Effects of using InGaZnO without annealing as buffer layer on the performance of InGaZnO thin film transistors

Contact Resistance of Electrodes in Tips-Pentacene OTFTs

Related Author

Yu-jie GAO

Peng JIANG

Ning ZHU

Yan ZHOU

Peng CHEN

Chao WANG

YE Yun

CHEN Li-wen

Related Institution

Wuhan BOE Optoelectronics Technology Co., Ltd.

College of Physics and Information Engineering, Fuzhou University

Xiamen Tianma Micro Electronics Co. LTD

Beijing BOE Display Technology Co., Ltd.

State Key Laboratory on Integrated Optoelectronics, Jilin University Region, College of Electronic Science and Engineering, Jilin University, Changchun 130012, China

AI问答

Address：No.3888 Dong Nanhu Road, Changchun, Jilin, China 130033 Postal code：130033
Tel：0431-86176059 Email：yjxs@ciomp.ac.cn
Technical support is provided by Beijing Founder electronics co., LTD 吉ICP备11002662号-17 京公网安备11010802024621
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰