Improvement research of via hole minimized by via hole etch conditions

LI Tian-sheng; CHEN Xu; XIE Zhen-yu; XU Shao-ying; MIN Tai-ye; ZHANG Xue-zhi

doi:10.3788/YJYXS20142905.0674

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Improvement research of via hole minimized by via hole etch conditions

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- Improvement research of via hole minimized by via hole etch conditions
- Chinese Journal of Liquid Crystals and Displays Vol. 29, Issue 5, Pages: 674-680(2014)
- 作者机构：
  
  北京京东方光电科技有限公司, 北京 100176
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20142905.0674
  CLC： TN141.9
- Received：01 January 2014，
  
  Revised：15 February 2014，
  
  Published Online：16 April 2013，
  
  Published：05 October 2014
- 稿件说明：
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李田生, 陈旭, 谢振宇, 徐少颖, 闵泰烨, 张学智. 过孔刻蚀工艺优化对过孔尺寸减小的研究[J]. 液晶与显示, 2014,29(5): 674-680

LI Tian-sheng, CHEN Xu, XIE Zhen-yu, XU Shao-ying, MIN Tai-ye, ZHANG Xue-zhi. Improvement research of via hole minimized by via hole etch conditions[J]. , 2014,29(5): 674-680
李田生, 陈旭, 谢振宇, 徐少颖, 闵泰烨, 张学智. 过孔刻蚀工艺优化对过孔尺寸减小的研究[J]. 液晶与显示, 2014,29(5): 674-680 DOI： 10.3788/YJYXS20142905.0674.

LI Tian-sheng, CHEN Xu, XIE Zhen-yu, XU Shao-ying, MIN Tai-ye, ZHANG Xue-zhi. Improvement research of via hole minimized by via hole etch conditions[J]. , 2014,29(5): 674-680 DOI： 10.3788/YJYXS20142905.0674.

摘要

为了适应TFT-LCD小型化与窄边框化以及在面板布线精细化的趋势，提高工艺设计富裕量以及增加面板的实际利用率，之前做过钝化层沉积工艺优化来减小液晶面板阵列工艺中连接像素电极与漏极的过孔尺寸的研究。本文在此基础上进行过孔刻蚀工艺的优化，从而最终达到进一步减小过孔尺寸实现TFT-LCD小型化与窄边框化的趋势。通过设计实验考察了影响过孔大小刻蚀主要影响因素（功率、压强、气体比率、刻蚀速率选择比）。实验结果表明，在薄膜沉积优化的基础上可使过孔的尺寸再降低10%~20%。对其进行了良率检测与工艺稳定性评价，最终获得了过孔尺寸减小的方案，并成功导入到产品生产中，从而提高了产品品质。

Abstract

In order to follow with the trend of miniaturization narrow frame and fine wiring structure

the TFT-LCD tends to develop for large margin of design and high real substrate utilization rate. The passivation layer deposit parameters were changed to decrease the size of via hole which connected the pixel electrode and drain electrode were studied on the previous articles. In this paper

based on the previous data

via hole etch process optimization were studied

and finally to get further improvement in hole size to meet the trend of miniaturization and narrow frame on TFT-LCD panel.The main parameters (power

pressure

gas ratio

etch rate ratio) to minimize via hole by etching process through the experiments design were studied. A solution to further minimize the via hole size about 10%~20% which refered to previous study was found. The array yield test and process stability test were evaluated.Finally

one better solution to minimize via hole size was obtained and applied into mass production.Therefore

the products quality was improved also.

关键词

Keywords

references

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Related Institution

Beijing BOE Optoelectronics Technology Co., Ltd

Faculty of Electronic and Information Engineering， Xi'an Jiaotong University

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Fujian Science & Technology Innovation Laboratory for Optoelectronic Information of China

College of Physics and Information Engineering， Fuzhou University

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