In order to realize the Timing Controller of TFT-LCD with Mini-LVDS interface based on FPGA

data arrangement of technology of Mini-LVDS and the timing controller of TFT-LCD

the function of FPGA are investigated.By studying data arrangement of Mini-LVDS

a special method of data processing was proposed. A parallel to serial converter was designed by using SRAM embedded in FPGA

the data in a row was divided into a front half part and a latter half part and the two parts of data were put out at the same time.The data of two adjacent points was turned from serial to parallel by using D trigger and the method of delay. By using shift register

serial adder and DDR technology

an 8:1 converter was designed and the data in a sub-pixel was turned from parallel to serial. Output Logic Macro cell in FPGA of Xilinx was used in the design of a data transmitter that turned the CMOS logic level signal into Mini-LVDS logic level signal. The problems of multiple clocks were discussed and solved by using clock macro blocks in FPGA of Xilinx. By studying the characteristics of Mini-LVDS and Timing Controller

the method of generating reset signal and the corresponding method of the data processing were presented.The timing controller of TFT-LCD with Mini-LVDS interface has been applied to products of our company with resolution of 1 2801 024

the frequency of its data is 108 MHz

and its color depth is 24 bit. The picture of the product is clear and natural.The timing controller of TFT-LCD can satisfy the system requirements of strong anti-jamming and stabilization.