Design of Driving Circuit for Area Array CCD Based on FPGA

ZHANG Chuan-sheng

doi:10.3788/YJYXS20122706.0789

您当前的位置：

首页 >

文章列表页 >

Design of Driving Circuit for Area Array CCD Based on FPGA

Driving & Controlling | 更新时间：2020-08-12

- Design of Driving Circuit for Area Array CCD Based on FPGA
- Chinese Journal of Liquid Crystals and Displays Vol. 27, Issue 6, Pages: 789-794(2012)
- 作者机构：
  
  中国科学院长春光学精密机械与物理研究所,吉林长春,中国,130033
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20122706.0789
  CLC： TN27
- Received：18 July 2012，
  
  Revised：16 August 2012，
  
  Published：15 December 2012
- 稿件说明：
移动端阅览
张传胜. 基于FPGA的面阵CCD驱动及快速显示系统的设计实现[J]. 液晶与显示, 2012,(6): 789-794

ZHANG Chuan-sheng. Design of Driving Circuit for Area Array CCD Based on FPGA[J]. , 2012,(6): 789-794
张传胜. 基于FPGA的面阵CCD驱动及快速显示系统的设计实现[J]. 液晶与显示, 2012,(6): 789-794 DOI： 10.3788/YJYXS20122706.0789.

ZHANG Chuan-sheng. Design of Driving Circuit for Area Array CCD Based on FPGA[J]. , 2012,(6): 789-794 DOI： 10.3788/YJYXS20122706.0789.

摘要

为了实现面阵CCD传感器采集的数据在TFT液晶屏上的快速显示

提出一种基于现场可编程逻辑门阵列(FPGA)的快速显示系统。利用FPGA构建软核处理器(NiosII)

采用专用IC模块AD9929作为CCD驱动与处理芯片

并依据TFT液晶屏和芯片AD9929的接口时序设计驱动电路

利用DMA技术实现采集数据的快速显示。电路的测试结果表明

利用该方法可以把面阵CCD传感器采集的数据快速显示在TFT液晶屏上

在工业现场监视场合具有广泛的实用性。

Abstract

In order to realize the speediness display collected by the area array CCD

a fast display system based on field-programmable gate array (FPGA) is presented. Using FPGA to build-up soft core processor and using appropriative IC module AD9929 as the driver processing chip of CCD

and then it designs the driver circuit according to the interface time order of TFT liquid crystal screen and chip AD9929. Finally

the speediness display of collected data can be realized through DMA technique. The testing results of circuit show that this method can make the collected data by area CCD rapidly display on the TFT liquid crystal screen

which has wide applications in the industrial field surveillance.

关键词

Keywords

references

王显军.基于SOC单片机的高集成度光电编码器电路设计 [J]. 光学精密工程, 2011,19(5):1082-1087.[2] 熊文彬,蒋泉,曲建军,等.基于FPGA实现的视频显示系统 [J]. 液晶与显示, 2011,26 (1):92-95.[3] 周维,何健鹰,聂菊根.CPLD和FPGA编程与配置的实现 [J]. 计算机与数字工程, 2006,34(1):100-102.[4] 毛剑慧,黑勇,吴斌,等.一种新颖的多模式FPGA配置方案 [J]. 微计算机信息, 2008,24(2):179-181.[5] 康艳霞,曹剑中,田雁,等.实时视频处理系统中乒乓缓存的设计 [J]. 弹箭与制导学报, 2007,24(1):218-221.[6] 常锋,孙志远,王瑞光,等.LED显示图像的非均匀度校正改进方法 [J]. 光学精密工程, 2011,19(4): 929-937.[7] 尹东辉,任彦楠,岳超,等.一种1024级灰度大电容负载的LCD驱动芯片设计 [J]. 液晶与显示, 2011,26 (1):78-82.[8] 潘应云,曾伟,陈家胜.基于ARM的智能显示终端 [J]. 电子测量技术, 2008,31 (1): 160-162.[9] 倪天龙,邓洪波,金连文.通过ADS7846在PDA上实现个性化书法输入 [J]. 电子技术应用, 2005,31 (6):65-67.

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Design of heterogeneous FPGA hardware accelerator based on CNN

Design and implementation of piecewise approximation bilateral filtering algorithm based on FPGA

Design of serial bus data distribution chip for LED display

Design of multi-channel real-time video processing system based on FPGA

Adaptive night scene enhancement system design and implementation based on FPGA

Related Author

JI Haolin

XU Wei

PIAO Yongjie

WU Xiaobin

GAO Tan

LIU Shiyu

ZHAO Xiadong

WEN Pan

Related Institution

Changchun Institute of Optics， Fine Mechanics and Physics， Chinese Academy of Sciences

University of Chinese Academy of Sciences

Key Laboratory of Space-based Dynamic & Rapid Optical Imaging Technology， Chinese Academy of Sciences

School of Microelectronics， Shanghai University

Key Laboratory of Advanced Display and System Applications of Ministry of Education， Shanghai University

AI问答

Address：No.3888 Dong Nanhu Road, Changchun, Jilin, China 130033 Postal code：130033
Tel：0431-86176059 Email：yjxs@ciomp.ac.cn
Technical support is provided by Beijing Founder electronics co., LTD 吉ICP备11002662号-17 京公网安备11010802024621
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰