LI Tuo, LI Qi-fen, LI Fu-le, CHEN Zhi-liang. Test and Improvement of Large Capacitor Load LCD Driver Chip[J]. , 2011,26(5): 620-625 DOI: 10.3788/YJYXS20112605.0620.
Test and Improvement of Large Capacitor Load LCD Driver Chip
large capacitor load LCD driver chip. The 12.5 MHz basic clock
control vectors for state change and frame frequency selection are provided by the FPGA
decreasing data is written to registers in the chip. With 200 pF capacitive load
the output signal range can realize 1 024 gray level and over 12 V voltage swing. Through testing the DAC and output buffer module in the chip
it is found that charging speed of the buffer to miller capacitor and the DAC to sampling capacitor cause the problem of longer full-swing rising/falling time and nonlinear output. It can be improved by reducing the on-chip convert resister or sampling capacitor to some extent. Finally
an improvement scheme is proposed
which uses switched-capacitor DAC and Class-AB output buffer error amplifier.
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references
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