Design of VLSI Architecture of 2-D Lifting Wavelet and FPGA Verification

MENG Wei; JIN Long-xu; HAN Shuang-li

doi:10.3788/YJYXS20112603.0404

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Design of VLSI Architecture of 2-D Lifting Wavelet and FPGA Verification

Imaging Technology & Image Processing | 更新时间：2020-08-12

- Design of VLSI Architecture of 2-D Lifting Wavelet and FPGA Verification
- Chinese Journal of Liquid Crystals and Displays Vol. 26, Issue 3, Pages: 404-408(2011)
- 作者机构：
  
  1. 中国科学院长春光学精密机械与物理研究所,吉林长春,中国,130033
  2. 中国科学院研究生院北京,100049
- 作者简介：
- 基金信息：
- DOI：10.3788/YJYXS20112603.0404
  CLC： TN911.73
- Received：19 August 2010，
  
  Revised：15 October 2010，
  
  Published Online：20 June 2011，
  
  Published：20 June 2011
- 稿件说明：
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孟伟, 金龙旭, 韩双丽. 二维提升小波的VLSI结构设计及FPGA验证[J]. 液晶与显示, 2011,26(3): 404-408

MENG Wei, JIN Long-xu, HAN Shuang-li. Design of VLSI Architecture of 2-D Lifting Wavelet and FPGA Verification[J]. , 2011,26(3): 404-408
孟伟, 金龙旭, 韩双丽. 二维提升小波的VLSI结构设计及FPGA验证[J]. 液晶与显示, 2011,26(3): 404-408 DOI： 10.3788/YJYXS20112603.0404.

MENG Wei, JIN Long-xu, HAN Shuang-li. Design of VLSI Architecture of 2-D Lifting Wavelet and FPGA Verification[J]. , 2011,26(3): 404-408 DOI： 10.3788/YJYXS20112603.0404.

摘要

针对JPEG2000中小波变换的硬件实现占用资源量大、速度慢等问题

提出了一种有效的二维小波硬件实现模型。该模型采用流水线并行结构

即对图像中各行像素进行流水线处理的同时

对小波分解的各级采用并行结构处理。这样的结构提高了小波变换的处理速度

实现了实时处理

节省了硬件的片上存储及外部存储资源。用FPGA对此模型进行验证。验证实验采用Xinlinx公司的SPARTEN-3系列芯片

对1 0242 048的大图像进行处理

图像处理速度达到 80 Mpixels/s

满足实时性要求。

Abstract

In order to save the resource and improve the speed of wavelet transform's hardware realization

an effective 2-dimension wavelet transform hardware structure has been proposed. This structure used parallel pipeline architecture

each layer of wavelet transform processed by parallel while pixels processed by pipeline. And the structure can improve the speed of wavelet transform

save the on-chip and external memory resource. It had been tested on Xilinx SPARTEN-3 series FPGA by processing large image with size 1 0242 048. Results showed the image processing speed could reach 80 Mpixel/s

meeting the real-time requirement.

关键词

Keywords

references

Tinku Acharya, Tsai Ping-Sing. JPEG2000 Standard for Image Compression: concept, algorithms and VLSI architectures [M].Canada: John Wiley & Sons, Inc., 2004:96-104.[2] 马伍新,崔占忠,代方震.用FPGA实现(5,3)小波变换 [J]. 计算机工程与设计, 2003, 24(1): 47-49.[3] Lian C J, Chen K F. Lifting based discrete wavelet transform architecture for JPEG2000 // Proceedings of the 2001 IEEE International Symposium on Circuits and Systems, New Jersey, USA:IEEE, 2001:445-448.[4] Movva S, Srinivasan S. A novel architecture for lifting based discrete wavelet transform for JPEG2000 standard suitable for VLSI implementation // Proceedings of 16th International Conference on VLSI Design, India: IEEE, 2003: 202-207.[5] Xiong C Y, Tian J W. The improved lifting scheme and novel reconfigurable VLSI architecture for the 5/3 and 9/7 wavelet filters //Proceedings of 2004 International Conference on Communications, Circuits and Systems, China:Chengdu:IEEE, 2004:728.[6] 田宝凤,徐抒岩,孙荣春,等.一种适合星上应用的遥感图像有损压缩算法 [J]. 光学精密工程, 2006, 14(4):725-730.[7] 王丽荣,申铉国,王延杰.基于提升方法的整数小波在DSP上的实现 [J]. 光学精密工程, 2004,12(2):187-188.[8] 朱珂,华林.应用于JPEG 2000 的高性能离散小波变换VLSI结构设计 [J]. 计算机辅助设计与图形学学报, 2004, 16(7):1010-1015.[9] 王承君,熊承义.二维5/3小波变换的FPGA结构设计与实现 [J]. 中南民族大学学报(自然科学版), 2006, 25(4):50-53.[10] 刘军伟,饶妮妮.提升小波变换的FPGA设计与实现 [J]. 微计算机信息, 2005, 21(10):132-134.

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