Design and implementation of FIR digital filter based on FPGA

Zhuo-da SONG; Zhi-qian WANG; Jian-rong LI; Cheng-wu SHEN; Shao-jin LIU

doi:10.37188/YJYXS20203510.1073

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Design and implementation of FIR digital filter based on FPGA

Display & Image Processing | 更新时间：2020-09-28

- Design and implementation of FIR digital filter based on FPGA
- Chinese Journal of Liquid Crystals and Displays Vol. 35, Issue 10, Pages: 1073-1078(2020)
- 作者机构：
  
  1.中国科学院长春光学精密机械与物理研究所, 吉林长春 130033
  2.中国科学院大学, 北京 100049
- 作者简介：
- 基金信息：
  
  Key Science and Technoloy Foundation of Jilin Province, China(20190302086GX);Key Science and Technoloy Foundation of Jilin Province, China(20200403067SF)
- DOI：10.37188/YJYXS20203510.1073
  CLC： TN911.72;TN713.7
- Received：09 April 2020，
  
  Revised：04 June 2020，
  
  Accepted：04 June 2020，
  
  Published：05 October 2020
- 稿件说明：
移动端阅览
Zhuo-da SONG, Zhi-qian WANG, Jian-rong LI, et al. Design and implementation of FIR digital filter based on FPGA[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1073-1078.
DOI：

Zhuo-da SONG, Zhi-qian WANG, Jian-rong LI, et al. Design and implementation of FIR digital filter based on FPGA[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1073-1078. DOI： 10.37188/YJYXS20203510.1073.

摘要

针对应变信号采集系统中的信号处理环节，设计并实现一种基于现场可编程门阵列（FPGA）的FIR数字滤波器。首先，基于Matlab采用克莱德曼窗函数设计一个长度为16的15阶数字滤波器，并生成高斯白噪声与频率为2 kHz、8 kHz正弦波的合成信号，然后量化12位系数，将系数文件导入QuartusⅡ13.1软件，结合FPGA内部数字滤波器IP核，采用自上而下的方式设计出FIR数字滤波器，最终在Simulink环境下对其进行仿真。实验结果表明，滤波前后合成信号的均方误差下降28.5%，提高了低频信号质量，增强了应变信号采集系统的功能性和集成度。

Abstract

A Finite Impulse Response(FIR) digital filter based on Field Programmable Gate Array(FPGA) is designed and implemented for signal processing in strain signal acquisition system. Firstly

based on MATLAB

Blackman window function is used to design a 15 order digital filter with 16 length

and the signal is composed of white Gaussian noise and sine wave with frequency of 2 kHz and 8 kHz. Then the 12 bit coefficients are quantized

and the coefficient file is imported into QuartusⅡ 13.1 software. Combining with the IP core of digital filter in FPGA

FIR digital filter is designed from top to bottom. Finally

it is simulated in Simulink environment. The results show that the mean square error of the synthesized signal decreases by 28.5% before and after filtering

which can improve the quality of low frequency signal and enhanced the function and integration of the strain signal acquisition system.

关键词

Keywords

references

魏国波.直升机旋转动部件载荷测试技术研究[D].西安: 西安电子科技大学, 2013. http://cdmd.cnki.com.cn/Article/CDMD-10701-1013295577.htm

WEI G B.The investigation in the Flight Test Technique of Rotary parts on helicopter[D]. Xi'an: Xidian University, 2013. (in Chinese)

黄学业 , 凌朝东 , 黄锐敏 , 等 . 基于FPGA的多路微弱医学生物电信号处理系统 . 液晶与显示 , 2014 . 29 ( 2 ): 245 - 250 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1698911&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1698911&Fpath=&index=-1&l=zh .

X Y HUANG , C D LING , R M HUANG , 等 . Multichannel weak medical bioelectrical signal processing system based on FPGA . Chinese Journal of Liquid Crystals and Display , 2014 . 29 ( 2 ): 245 - 250 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1698911&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1698911&Fpath=&index=-1&l=zh .

杜勇 . 数字滤波器的MATLAB与FPGA实现 , 2版 : 北京电子工业出版社 , 2014 .

Y DU . MATLAB and FPGA Implementation of Digital Filter , 2nd ed : Beijing Publishing House of Electronics Industry , 2014 .

卢雍卿 , 李剑文 , 许雯雯 , 等 . 基于FPGA的数字滤波器设计与仿真 . 软件导刊 , 2017 . 16 ( 2 ): 85 - 88 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=rjdk201702026 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=rjdk201702026 .

Y Q LU , J W LI , W W XU , 等 . Design and simulation of digital filter based on FPGA . Software Guide , 2017 . 16 ( 2 ): 85 - 88 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=rjdk201702026 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=rjdk201702026 .

安都勋 , 霍建华 , 王留全 . 基于MAX1452的应变测试系统前端模块的设计 . 电子设计工程 , 2012 . 20 ( 2 ): 118 - 120 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201202041 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201202041 .

D X AN , J H HUO , L Q WANG . Design of strain testing system front-end module based on MAX1452 . Electronic Design Engineering , 2012 . 20 ( 2 ): 118 - 120 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201202041 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201202041 .

罗杰 . Verilog HDL与FPGA数字系统设计: Quartus Ⅱ , : 北京机械工业出版社 , 2015 .

J LUO . Design of Verilog HDL and FPGA Digital System Quartus Ⅱ , : Beijing China Machine Press , 2015 .

王艳芬 , 张晓光 , 王刚 , 等 . 关于FIR滤波器窗函数设计法的若干问题讨论 . 电气电子教学学报 , 2017 . 39 ( 2 ): 83 - 88 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dqdzjxxb201702025 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dqdzjxxb201702025 .

Y F WANG , X G ZHANG , G WANG , 等 . Discussion on some problems about the design of window function of FIR filter . Journal of Electrical & Electronic Education , 2017 . 39 ( 2 ): 83 - 88 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dqdzjxxb201702025 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dqdzjxxb201702025 .

刘福泉.基于FPGA的FIR数字滤波器实现[D].北京: 北京邮电大学, 2012. http://d.wanfangdata.com.cn/Thesis/Y346264

LIU F Q. Implementation of FIR digital filter based on FPGA[D]. Beijing: Beijing University of Posts and Telecommunications, 2012. (in Chinese)

郭晓伟 , 陈钟荣 , 夏利娜 . 基于FPGA的高速高阶FIR滤波器的频域改进方法 . 现代电子技术 , 2016 . 39 ( 11 ): 55 - 58, 62 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=xddzjs201611014 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=xddzjs201611014 .

X W GUO , Z R CHEN , L N XIA . Frequency domain improvement method for high-speed and high-order FIR filter based on FPGA . Modern Electronics Technique , 2016 . 39 ( 11 ): 55 - 58, 62 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=xddzjs201611014 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=xddzjs201611014 .

王辉 . FIR数字滤波器的设计与研究 . 装备制造技术 , 2018 . ( 1 ): 48 - 49, 62 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zbzzjs201801015 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zbzzjs201801015 .

H WANG . Design and research of FIR digital filter . Equipment Manufacturing Technology , 2018 . ( 1 ): 48 - 49, 62 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zbzzjs201801015 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zbzzjs201801015 .

陈媛媛 , 刘有耀 . FIR滤波器的FPGA设计与实现 . 电子设计工程 , 2017 . 25 ( 24 ): 65 - 69, 73 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201724015 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201724015 .

Y Y CHEN , Y Y LI . FIR filter of the FPGA design and implementation . Electronic Design Engineering , 2017 . 25 ( 24 ): 65 - 69, 73 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201724015 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=dzsjgc201724015 .

李亮.基于Simulink的软件无线电硬件协同仿真技术[D].成都: 电子科技大学, 2013. http://cdmd.cnki.com.cn/Article/CDMD-10614-1013333729.htm

LI L. Simulink-based software radio hardware co-simulation technology[D]. Chengdu: University of Electronic Science and Technology of China, 2013. (in Chinese)

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