Influence of gate profile on TFT manufacturing process

Dan LIU; Yi LIU; Zhong-hao HUANG; Kun-kun GAO; Xu WU; Mao-kun TIAN; Kai WANG; Chao ZHANG; Rui WANG; Tai-ye MIN; Jia-hai FENG; Liang FANG

doi:10.37188/YJYXS20203510.1026

您当前的位置：

首页 >

文章列表页 >

Influence of gate profile on TFT manufacturing process

Device Physics & Device Preparation | 更新时间：2020-09-28

- Influence of gate profile on TFT manufacturing process
- Chinese Journal of Liquid Crystals and Displays Vol. 35, Issue 10, Pages: 1026-1035(2020)
- 作者机构：
  
  1.重庆京东方光电科技有限公司, 重庆 400700
  2.重庆大学物理学院, 重庆 400044
  3.中国科学院重庆绿色智能技术研究院, 重庆 400714
- 作者简介：
- 基金信息：
- DOI：10.37188/YJYXS20203510.1026
  CLC： TN304;TN141.9
- Received：20 March 2020，
  
  Revised：14 May 2020，
  
  Accepted：14 May 2020，
  
  Published：05 October 2020
- 稿件说明：
移动端阅览
Dan LIU, Yi LIU, Zhong-hao HUANG, et al. Influence of gate profile on TFT manufacturing process[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1026-1035.
DOI：

Dan LIU, Yi LIU, Zhong-hao HUANG, et al. Influence of gate profile on TFT manufacturing process[J]. Chinese journal of liquid crystals and displays, 2020, 35(10): 1026-1035. DOI： 10.37188/YJYXS20203510.1026.

摘要

薄膜晶体管（Thin film transistor，TFT）的栅极在截面方向上是一个台阶，栅极绝缘层（Gate Insulator，GI）和源漏极（Source和Data电极，SD电极）依次覆盖于台阶之上，覆盖程度以台阶覆盖率（台阶处GI层水平厚度与竖直厚度的比值）进行衡量。本文结合重庆京东方的HADS产品工艺制程，探究了栅极厚度、坡度角对GI层的台阶覆盖率的影响。同时，在覆盖率的基础上研究了台阶处和非台阶处的SD膜层刻蚀程度差异。结合量产中的不良，分析栅极坡度角、覆盖率、栅极腐蚀等相关不良的关系，并提出相应的良率提升措施。实验结果表明：坡度角是影响GI覆盖率的关键因素，且栅极坡度角与GI覆盖率呈负线性关系。当栅极厚度在280~500 nm范围变化时，栅极坡度角每增加10°，GI层台阶覆盖率下降约20%。SD膜层覆盖在台阶上，因台阶的存在造成此处的SD层减薄，最终导致该处的SD膜层刻蚀程度加大。如果栅极坡度角偏大，会导致台阶处GI层减薄或者产生微裂纹，工艺制程中的腐蚀介质会透过减薄的GI层进而腐蚀栅极；此外，偏大的栅极坡度角会导致台阶处的SD电极有断线的风险。通过刻蚀液种类变更、刻蚀液成分微调、刻蚀工艺的优化可以降低栅极坡度角，规避上述良率风险。此外，对于栅极腐蚀型不良，也可以通过调整GI层的成膜参数来提升覆盖率。对于SD电极断线风险，可尝试增加光刻胶粘附力、台阶处SD线加宽等措施规避风险。

Abstract

The gate electrode of thin film transistor(TFT) is a step in cross section

it is covered by gate insulator(GI)

source and data electrode(SD electrode) in sequence

and the degree of coverage is measured by the step coverage

which is the ratio of the horizontal thickness to the vertical thickness of GI layer at the step. In this paper

combining the manufacturing process of HADS product in Chongqing BOE company

the influence of gate thickness and profile on the GI layer step coverage is studied. Then

the difference of SD etching degree between step and non-step is explored based on step coverage. After that

the relationship between gate profile

step coverage

Cu corrosion and other defects are analyzed based on defect information in mass production. At last

the corresponding yield up measures are proposed. The experimental results show that the tate profile is a key factor affecting step coverage

and gate profile has a negative linear relationship with GI coverage. When the gate thickness varies from 280 nm to 500 nm

the GI coverage decreases by 20% for every 10° increase in the gate profile. SD layer covers the step

and will be thinned at this place

which leads to an increase in the degree of SD etching. If the gate profile is large

the GI layer at the step will be thinned or generates micro-cracks

the corrosive medium in manufacturing process will pass through the thinned GI layer or crack to react with gate electrode to form corrosion. Whats more

a larger gate profile will cause SD line to be open at the step. A gentle gate profile can be obtained to avoid the above yield risk by changing etchant

adjusting etchant composition

optimizing etch process. In addition

it is a useful method to adjust GI deposition parameter to improve GI coverage to avoid gate corrosion; and the solution containing improving photo-resist adhesion

widening the SD line at the step can be tried to avoid SD line open.

关键词

Keywords

references

李继军 , 聂晓梦 , 李根生 , 等 . 平板显示技术比较及研究进展 . 中国光学 , 2018 . 11 ( 5 ): 695 - 710 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zggxyyygxwz201805001 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zggxyyygxwz201805001 .

J J LI , X M NIE , GS LI , 等 . Comparison and research progress of flat panel display technology . Chinese Optics , 2018 . 11 ( 5 ): 695 - 710 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zggxyyygxwz201805001 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=zggxyyygxwz201805001 .

李继军 , 聂晓梦 , 甄威 , 等 . 显示技术比较及新进展 . 液晶与显示 , 2018 . 33 ( 1 ): 74 - 84 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377207&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377207&Fpath=&index=-1&l=zh .

J J LI , X M NIE , W ZHEN , 等 . New developments and comparisons in display technology . Chinese Journal of Liquid Crystals and Displays , 2018 . 33 ( 1 ): 74 - 84 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377207&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377207&Fpath=&index=-1&l=zh .

吴诗聪 . Mini-LED:助力下一轮LCD技术发展 . 光电子技术 , 2018 . 38 ( 3 ): 145 - 148 . http://www.cqvip.com/QK/93184X/201803/676774633.html http://www.cqvip.com/QK/93184X/201803/676774633.html .

S C WU . Mini-LED:next round of LCD evolution . Optoelectronic Technology , 2018 . 38 ( 3 ): 145 - 148 . http://www.cqvip.com/QK/93184X/201803/676774633.html http://www.cqvip.com/QK/93184X/201803/676774633.html .

林致远 , 杨成绍 , 邹志翔 , 等 . ITO像素电极工序对于HADS产品TFT特性的影响 . 液晶与显示 , 2016 . 31 ( 4 ): 370 - 374 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1706549&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1706549&Fpath=&index=-1&l=zh .

Z Y LIN , C S YANG , Z X ZOU , 等 . Effects of pixel ITO process on TFT characteristics of HADS product . Chinese Journal of Liquid Crystals and Displays , 2016 . 31 ( 4 ): 370 - 374 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1706549&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1706549&Fpath=&index=-1&l=zh .

刘丹 , 秦刚 , 蔡卫超 , 等 . Mo/Al/Mo结构电极的坡度角和关键尺寸差研究 . 液晶与显示 , 2017 . 32 ( 11 ): 877 - 885 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1376513&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1376513&Fpath=&index=-1&l=zh .

D LIU , G QIN , W C CAI , 等 . Profile and critical dimension bias of Mo/Al/Mo electrode . Chinese Journal of Liquid Crystals and Displays , 2017 . 32 ( 11 ): 877 - 885 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1376513&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1376513&Fpath=&index=-1&l=zh .

谢振宇. a-Si TFT用氮化硅薄膜的制备及其性能研究[D].成都: 电子科技大学, 2006.

XIE Z Y. Preparition cond properties of silicon nitride thin films for a-Si TFT[D]. Chengdn: Universiting of Erectronic science and Technology. (in CHinese)

S OSONO , Y UCHIYAMA , M KITAZOE , 等 . Coverage properties of silicon nitride film prepared by the Cat-CVD method . Thin Solid Films , 2003 . 430 ( 1/2 ): 165 - 169 . http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=0aa9f408159c58b596c5c140fbda9aa6 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=0aa9f408159c58b596c5c140fbda9aa6 .

A HEYA , T MINAMIKAWA , T NIKI , 等 . Coverage properties of SiN x films prepared by catalytic chemical vapor deposition on trenched substrates below 80℃ . Thin Solid Films , 2008 . 516 ( 10 ): 3000 - 3004 . DOI: 10.1016/j.tsf.2007.11.001 http://doi.org/10.1016/j.tsf.2007.11.001 .

白金超 , 李小龙 , 韩皓 , 等 . 4-Mask工艺Cu腐蚀分析及改善研究 . 液晶与显示 , 2019 . 34 ( 2 ): 125 - 129 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1381879&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1381879&Fpath=&index=-1&l=zh .

J C BAI , X L LI , H HAN , 等 . Research of Cu corrosion in 4-Mask process . Chinese Journal of Liquid Crystals and Displays , 2019 . 34 ( 2 ): 125 - 129 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1381879&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1381879&Fpath=&index=-1&l=zh .

刘丹 , 秦刚 , 王任远 , 等 . 阵列基板栅极制程的Cu腐蚀研究 . 液晶与显示 , 2018 . 33 ( 9 ): 717 - 724 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1379072&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1379072&Fpath=&index=-1&l=zh .

D LIU , G QIN , R Y WANG , 等 . Cu corrosion of array substrate in gate process . Chinese Journal of Liquid Crystals and Displays , 2018 . 33 ( 9 ): 717 - 724 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1379072&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1379072&Fpath=&index=-1&l=zh .

马群刚 , 周刘飞 , 喻玥 , 等 . InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究 . 物理学报 , 2019 . 68 ( 10 ): 108501 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201910033 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201910033 .

Q G MA , L F ZHOU , Y YU , 等 . Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane . Acta Physica Sinica , 2019 . 68 ( 10 ): 108501 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201910033 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201910033 .

马群刚 , 王海宏 , 张盛东 , 等 . InGaZnO薄膜晶体管背板的层间Cu互连静电保护研究 . 物理学报 , 2019 . 68 ( 15 ): 158501 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201915022 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201915022 .

Q G MA , H H WANG , D ZHANGS , 等 . Electro-static discharge protection analysis and design optimization of interlayer Cu interconnection in InGaZnO thin film transistor backplane . Acta Physica Sinica , 2019 . 68 ( 15 ): 158501 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201915022 http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=wlxb201915022 .

范学丽 , 靖瑞宽 , 王晏酩 , 等 . TFT-LCD制造工艺中金属或金属复合膜层坡度角的研究 . 液晶与显示 , 2018 . 33 ( 3 ): 208 - 212 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377810&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377810&Fpath=&index=-1&l=zh .

X L FAN , R K JING , YM WANG , 等 . TFT-LCD manufacture technology metal or metal composite film layer profile . Chinese Journal of Liquid Crystals and Displays , 2018 . 33 ( 3 ): 208 - 212 . http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377810&Fpath=&index=-1&l=zh http://cjlcd.lightpublishing.cn/thesisDetails?columnId=1377810&Fpath=&index=-1&l=zh .

Views

204

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Mechanism analysis and suppression measures for gate data short defects in oxide TFT

Improving circuit design for the stability of inverters based on amorphous indium gallium zinc oxide thin film transistors

Research progress on crystalline IGZO thin film transistor

Effect of sputtering power on properties of W-doped ZnO thin film transistors

Effect of oxygen to argon ratio on the electrical performance of Ta₂O₅ gate dielectric thin film transistor

Related Author

LIU Dan

FAN Xiaojun

CEHN Wei

LIU Wei

LIU Chuan

DU Hongwei

YANG Sheng

WU Xu

Related Institution

BOE Technology Group Co. Ltd.

School of Electronics and Information Technology， Sun Yat-sen University

Lennovo PCSD Quality Technology Committee

Chongqing BOE Optoelectronics Technology Co. Ltd.

Department of Electronic Engineering， Shanghai Jiao Tong University

AI问答

Address：No.3888 Dong Nanhu Road, Changchun, Jilin, China 130033 Postal code：130033
Tel：0431-86176059 Email：yjxs@ciomp.ac.cn
Technical support is provided by Beijing Founder electronics co., LTD 吉ICP备11002662号-17 京公网安备11010802024621
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰