Design for AMOLED source driver output buffer with DAC function

Rui SUN; Hong-hui DENG; Jun ZHANG; Lei QUAN; Chen JIA

doi:10.37188/YJYXS20203509.0938

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Design for AMOLED source driver output buffer with DAC function

Driving Circuits | 更新时间：2020-09-08

- Design for AMOLED source driver output buffer with DAC function
- Chinese Journal of Liquid Crystals and Displays Vol. 35, Issue 9, Pages: 938-945(2020)
- 作者机构：
  
  1.合肥工业大学微电子设计研究所, 安徽合肥 230009
  2.深圳清华大学研究院, 广东深圳 518057
- 作者简介：
- 基金信息：
  
  Key Laboratory Fund Project(6142802180101)
- DOI：10.37188/YJYXS20203509.0938
  CLC： TP394.1;TH691.9
- Received：03 February 2020，
  
  Revised：05 March 2020，
  
  Accepted：05 March 2020，
  
  Published：05 September 2020
- 稿件说明：
移动端阅览
Rui SUN, Hong-hui DENG, Jun ZHANG, et al. Design for AMOLED source driver output buffer with DAC function[J]. Chinese journal of liquid crystals and displays, 2020, 35(9): 938-945.
DOI：

Rui SUN, Hong-hui DENG, Jun ZHANG, et al. Design for AMOLED source driver output buffer with DAC function[J]. Chinese journal of liquid crystals and displays, 2020, 35(9): 938-945. DOI： 10.37188/YJYXS20203509.0938.

摘要

针对AMOLED驱动芯片小面积、高精度、低功耗的需求，设计了一种具有DAC功能的高性能输出缓冲器。该缓冲器采用轨对轨的输入级和Class AB输出级以适应大的输入输出电压范围，采用Cascode Miller补偿以减小补偿电容大小，其尾电流源可编程以实现4 bit DAC功能插值，节约了整体功耗和芯片面积。在UMC80 nm CMOS工艺下，仿真结果表明，在0.2~6.3 V的输入电压范围内，缓冲器直流增益大于70 dB，相位裕度大于60°，静态电流最小可至0.5 μA，建立时间低至1.49 μs；典型中压3.3 V的情况下，直流增益可达129 dB，相位裕度为75°，增益带宽为9.4 MHz，静态电流为1.3 μA；对60 mV输入电压进行4 bit插值后，输出误差小于0.255 mV。设计的缓冲器精度高、建立时间快且功耗低，输出缓冲器实现了第二级DAC的作用，满足了AMOLED源极驱动的应用需求。

Abstract

To meet the requirements of small area

high precision and low power consumption of AMOLED driver chip

a high performance output buffer with DAC function is designed. This buffer adopts rail-to-rail input stage and Class AB output stage to adapt to a large input and output voltage range

and uses Cascode Miller compensation to reduce the size of the compensation capacitor. Its tail current source is programmable to implement 4 bit DAC function interpolation

saving overall power consumption and chip area. Under the UMC80 nm CMOS process

the simulation results show that in the input voltage range of 0.2~6.3 V

the DC gain of the buffer is greater than 70 dB

the phase margin is greater than 60°

the quiescent current can be as low as 0.5 μA

and the settling time as low as 1.49 μs. With a typical medium voltage of 3.3 V

the DC gain can reach 129 dB

the phase margin is 75°

the gain bandwidth is 9.4 MHz

and the quiescent current is 1.3 μA. After 4 bit interpolation of the 60 mV input voltage

the output error is less than 0.255 mV. The designed buffer has high accuracy

fast settling time

and low power consumption. The output buffer realizes the role of the second-stage DAC

which meets the application requirements of AMOLED source driving.

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references

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Engineering Research Center of Embedded System Integration, Ministry of Education, Northwestern Polytechnical University, Xi'an 710072,China, E-mail: liuxings@yahoo.

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