Influence of MOS transistor size on data writing in digital driving pixel circuit of OLED-on-silicon

Yong XU; Peng-he QI; Ran HUANG; Bo-hua ZHAO; Meng-xin LIU

doi:10.37188/CJLCD.2020-0357

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Influence of MOS transistor size on data writing in digital driving pixel circuit of OLED-on-silicon

Driving and Controlling | 更新时间：2021-04-28

- Influence of MOS transistor size on data writing in digital driving pixel circuit of OLED-on-silicon
- Chinese Journal of Liquid Crystals and Displays Vol. 36, Issue 5, Pages: 680-686(2021)
- 作者机构：
  
  1.中国科学院大学, 北京 100049
  2.中国科学院微电子研究所, 北京 100029
  3.中国科学院硅器件技术重点实验室, 北京 100029
- 作者简介：
- 基金信息：
- DOI：10.37188/CJLCD.2020-0357
  CLC： TP394.1;TN27
- Received：04 January 2021，
  
  Revised：18 January 2021，
  
  Published：2021-05
- 稿件说明：
移动端阅览
Yong XU, Peng-he QI, Ran HUANG, et al. Influence of MOS transistor size on data writing in digital driving pixel circuit of OLED-on-silicon[J]. Chinese journal of liquid crystals and displays, 2021, 36(5): 680-686.
DOI：

Yong XU, Peng-he QI, Ran HUANG, et al. Influence of MOS transistor size on data writing in digital driving pixel circuit of OLED-on-silicon[J]. Chinese journal of liquid crystals and displays, 2021, 36(5): 680-686. DOI： 10.37188/CJLCD.2020-0357.

摘要

以传统的6T SRAM（5T+1MOS驱动管）结构硅基OLED像素电路为例，分析了开关管尺寸对数据写入的影响。提出了一种新型数字型硅基OLED像素电路，用5T（4T+1MOS驱动管）实现与6T SRAM（5T+1MOS驱动管）结构相同的功能。另外新型的像素电路与传统的SRAM结构相比，其数据写入不受开关管尺寸的影响，可以采用最小尺寸的开关管。基于SMIC 0.18 μm 1.8 V/5 V混合信号工艺设计，通过仿真得出6T SRAM结构像素电路能正常写入的开关管最小尺寸为540 nm/600 nm，像素单元版图面积为4.3 μm×4.3 μm；新型5T结构像素电路中的开关管尺寸可以为工艺最小尺寸，即300 nm/600 nm，版图面积为3.91 μm×3.91 μm，相比之下单个像素单元版图面积缩小了17.3%。

Abstract

The traditional 6T SRAM (5T and a driving MOS transistor) OLED-on-silicon pixel circuit is taken as an example to analyze the influence of switch size on data writing. A novel digital OLED-on-silicon pixel circuit is proposed

which uses 5T (4T and a driving MOS transistor) to achieve the same function as 6T SRAM (5T and a driving MOS transistor). In addition

compared with the traditional SRAM structure

the data writing of the new pixel circuit is not affected by the switch size

and the smallest switch size can be used. Based on SMIC 0.18 μm 1.8 V/5 V mixed signal process design

the simulation results show that the minimum size of the switch in 6T SRAM pixel circuit is 540 nm/600 nm

and the pixel unit layout area is 4.3 μm×4.3 μm. The switch in new 5T pixel circuit can be the minimum size of the process

that is

300 nm/600 nm

and the layout area is 3.91 μm×3.91 μm. In contrast

the area of a single pixel unit layout is reduced by 17.3%.

关键词

Keywords

references

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