Design of dual-port video buffer based on FPGA

TANG Bin

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Design of dual-port video buffer based on FPGA

更新时间：2020-08-12

- Design of dual-port video buffer based on FPGA
- Chinese Journal of Liquid Crystals and Displays Vol. 29, Issue 4, Pages: 575-579(2014)
- 作者机构：
  
  贵州财经大学信息学院, 贵州贵阳 550025
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP333
- Received：14 October 2013，
  
  Revised：23 January 2014，
  
  Published：05 August 2014
- 稿件说明：
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唐斌. 基于FPGA的双端口视频缓冲器设计[J]. 液晶与显示, 2014,29(4): 575-579

TANG Bin. Design of dual-port video buffer based on FPGA[J]. , 2014,29(4): 575-579
唐斌. 基于FPGA的双端口视频缓冲器设计[J]. 液晶与显示, 2014,29(4): 575-579 DOI：

TANG Bin. Design of dual-port video buffer based on FPGA[J]. , 2014,29(4): 575-579 DOI：

摘要

介绍一种基于FPGA和SDRAM的双端口的视频缓冲器设计方法。使用小容量的同步FIFO和异步FIFO串联构成用户接口，采用分块方式读写单块存储器SDRAM，采用混合算法合理仲裁读、写和刷新请求，实现单路视频数据的实时采集和输出。本系统设计简单，调试方便。只需适当地改变数据块的长度和FIFO的容量就可以应用于其他的视频处理系统。仿真测试结果表明：SDRAM时钟频率工作在71 MHz下可以确保视频流的流畅性。而且通过改变FIFO的相关参数，还可以继续提高SDRAM的实际带宽。本设计还具有一定的灵活性。

Abstract

The design of dual-port video buffer based on FPGA and SDRAM is introduced. The user interfaces are composed of small capacity synchronous FIFO and asynchronous FIFO in series connection. The SDRAM is accessed in burst mode. The arbitrator uses a modified algorithm to grant the right to use the bus of SDRAM. The single memory can store the captured data and provide data for displaying simultaneously. Experimental results indicate when SDRAM works in 71 MHz

there are no error in the video data transmission. This system is simple and easy to be debugged. By changing relevant parameters of FIFOs and length of the block

the actual bandwidth of SDRAM can achieve a high performance.

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references

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