Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions

LI Tian-sheng; XIE Zhen-yu; ZHANG Wen-yu; YAN Chang-jiang; XU Shao-ying; CHEN Xu; MIN Tai-

doi:null

您当前的位置：

首页 >

文章列表页 >

Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions

Device Physics & Device Technology | 更新时间：2020-08-12

- Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions
- Chinese Journal of Liquid Crystals and Displays Vol. 27, Issue 4, Pages: 493-498(2012)
- 作者机构：
  
  北京京东方光电科技有限公司北京,100176
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN141.9
- Received：14 February 2012，
  
  Revised：17 May 2012，
  
  Published Online：15 August 2012，
  
  Published：15 August 2012
- 稿件说明：
移动端阅览
李田生, 谢振宇, 张文余, 阎长江, 徐少颖, 陈旭, 闵泰烨, 苏顺康. 钝化层沉积工艺对过孔尺寸减小的研究[J]. 液晶与显示, 2012,(4): 493-498

LI Tian-sheng, XIE Zhen-yu, ZHANG Wen-yu, YAN Chang-jiang, XU Shao-ying, CHEN Xu, MIN Tai-ye, SU Shun-kang. Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions[J]. , 2012,(4): 493-498
李田生, 谢振宇, 张文余, 阎长江, 徐少颖, 陈旭, 闵泰烨, 苏顺康. 钝化层沉积工艺对过孔尺寸减小的研究[J]. 液晶与显示, 2012,(4): 493-498 DOI：

LI Tian-sheng, XIE Zhen-yu, ZHANG Wen-yu, YAN Chang-jiang, XU Shao-ying, CHEN Xu, MIN Tai-ye, SU Shun-kang. Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions[J]. , 2012,(4): 493-498 DOI：

摘要

为了适应TFT-LCD小型化与窄边框化以及在面板布线精细化的趋势

提高工艺设计富裕量以及增加面板的实际利用率

研究了通过改变钝化层(PVX)的沉积工艺来减小液晶面板阵列工艺中连接像素电极与漏极的过孔(VIA)尺寸的方案

通过设计实验考察了影响过孔大小的钝化层的主要影响因素(黑点、倒角、顶层钝化层沉积厚度

顶层钝化层沉积压力)

得出了在不改变原有刻蚀方式基础之上使过孔的尺寸降低20%~30%的优化方案

并对其进行了电学性能评价(

:开态电流、

off

:关态电流、

:阈值电压、Mobility:迁移率)

从而获得了较佳的减小过孔尺寸的方案

提高了产品品质。

Abstract

In the trend of miniaturization narrow frame and fine wiring structure

the TFT-LCD tends to developing for large margin of design and high real substrate utilization rate. The passivation layer deposit parameters were changed to decrease the size of via hole which connected the pixel electrode and drain electrode were studied. Through the experiments design of changing main parameters to minimize via hole of passivation layer(haze

undercut

Top-PVX deposit thickness

Top-PVX deposit pressure)

a solution to minimize the via hole about 20%~30% without changing the etch conditions was found. The electronic parameter measurement was evaluated (

off

Mobility) and finally one better solution to minimize via hole size was obtained. Therefore

the products quality was improved also.

关键词

Keywords

references

周伟峰,薛建设.应用低介电材料丙烯酸酯树脂作为TFT-LCD的钝化层材料[J]. 液晶与显示, 2011,26(1):19-22.[2] 姚建可,许宁生,邓少芝,等. 塑料基底a-Si :H TFT制备技术 [J]. 液晶与显示, 2010,25(4): 543-545.[3] 董杰,金相起,朴范求,等. a-Si TFT LCD过孔尺寸的缩减 [J]. 液晶与显示, 2008,23(6):688-691.[4] Pham T T Pham, Lee J H, Kim Y S, et al. Properties of SixNy thin film deposited by plasma enhanced chemical vapor deposition at low temperature using SiH4/NH3/Ar as barrier film [J].Surface and Coatings Technology, 2008(202):5617-5620.[5] 李新贝,张方辉,牟强,等.离子增强化学气相沉积条件对氮化硅薄膜性能的影响 [J]. 材料保护, 2006,(7):12-16.[6] Ali S, Gharghi M, Sivoththaman S. Properties and characterization of low temperature amorphous PECVD silicon nitride films for solar cell passivation [J].J. Mater. Sci., 2005,(40):1469-1473.[7] 于映,陈抗生. 氮化硅薄膜的PECVD生长及其性能研究 [J]. 真空电子技术, 1996,(2):16-18.[8] 谢振宇,龙春平,邓朝勇,等. 非晶硅TFT栅界面层氮化硅薄膜性能的研究 [J]. 真空科学与技术学报, 2007,(4):341-345.[9] Mackel H, Ludemann R. Study of the composition of hydrogenated SiNx layers for high-quality silicon surface passivation [J].Appl. Phys., 2002, 92(5):2602-2607.

Views

121

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Improvement research of via hole minimized by via hole etch conditions

Fabrication of high-resolution active matrix driven GaN-based Micro-LED chips

TFT-LCD manufacture technology metal or metal composite film layer profile

Analysis and improvement of vertical line mura

Influence factors of high thickness ITO residual in TFT process

Related Author

ZHANG Xue-zhi

GUO Tai-liang

HUANG Ming-shui

NIE Jun-yang

LIU Ming-yang

LI Yang

PAN Kui

DENG Li-ying

Related Institution

Beijing BOE Optoelectronics Technology Co., Ltd, Beijing 100176, China

Faculty of Electronic and Information Engineering， Xi'an Jiaotong University

Rich Sense Electronics Technology Co.， Ltd.

Fujian Science & Technology Innovation Laboratory for Optoelectronic Information of China

College of Physics and Information Engineering， Fuzhou University

AI问答

Address：No.3888 Dong Nanhu Road, Changchun, Jilin, China 130033 Postal code：130033
Tel：0431-86176059 Email：yjxs@ciomp.ac.cn
Technical support is provided by Beijing Founder electronics co., LTD 吉ICP备11002662号-17 京公网安备11010802024621
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰