FPGA Realization of Video Image Zooming Display

SUN Hong-jin

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FPGA Realization of Video Image Zooming Display

Imaging Technology & Image Processing | 更新时间：2020-08-12

- FPGA Realization of Video Image Zooming Display
- Chinese Journal of Liquid Crystals and Displays Vol. 25, Issue 1, Pages: 130-133(2010)
- 作者机构：
  
  南京工业大学信息科学与工程学院,江苏南京 210009,E-mail: sunhjin@yeah.net
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP301.6
- Received：26 June 2009，
  
  Revised：02 January 1900，
  
  Published Online：20 February 2010，
  
  Published：20 February 2010
- 稿件说明：
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孙红进. FPGA实现的视频图像缩放显示[J]. 液晶与显示, 2010,25(1): 130-133

SUN Hong-jin. FPGA Realization of Video Image Zooming Display[J]. 液晶与显示, 2010,25(1): 130-133
孙红进. FPGA实现的视频图像缩放显示[J]. 液晶与显示, 2010,25(1): 130-133 DOI：

SUN Hong-jin. FPGA Realization of Video Image Zooming Display[J]. 液晶与显示, 2010,25(1): 130-133 DOI：

摘要

对几种常用的图像缩放算法进行了比较

在权衡了算法复杂度、缩放效果和FPGA逻辑资源等3大因素后

选择了双线性插值算法来实现图像缩放。重点介绍了双线性插值算法和该方法的FPGA硬件实现方法

包括图像数据缓冲单元、插值系数生成单元以及插值计算单元等。应用结果表明

双线性插值算法及其硬件实现模块达到了预期的效果。

Abstract

Some commonly used image scaling algorithms were introduced

as well as a comparison among several algorithms. After weighing the algorithm complexity

zoom effects and FPGA logic resources

etc.

the bilinear interpolation algorithm was chosen to achieve image scaling. This work focused on the bilinear interpolation algorithm and the method of FPGA hardware implementation

including image data buffer unit

interpolation coefficient generating unit

as well as the interpolation calculation unit. The realized results show that the bilinear interpolation algorithm and its hardware realizing modules achieve the desired results.

关键词

Keywords

references

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