The application of histogram equalization enhancement algorithms in display system is introduced. Real-time parallel processing of batches data of FPGA (Programmable Logic Device) is used in achieving histogram equalization enhancement. Compared with the traditional DSP method
the advantage of this system is noticeable in real-time image processing and work efficiency.The implementing method of the main function module is provided. The system is simple
compact and reliable.
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references
. 冈萨雷斯. 数字图像处理 [M] 北京:电子工业出版社,2004.
. 吴继华. Altera FPGA/CPLD 设计(高级篇) [M]. 北京:人民邮电出版社,2005.