Design of FPGA-Based High Frame Rate Driving Circuit for Array CCD

SHANG Xiao-chuan; ZHOU Hui; ZHANG Xing-xiang; REN Jian-yue

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Design of FPGA-Based High Frame Rate Driving Circuit for Array CCD

Imaging Technology & Image Processing | 更新时间：2020-08-12

- Design of FPGA-Based High Frame Rate Driving Circuit for Array CCD
- Chinese Journal of Liquid Crystals and Displays Vol. 24, Issue 5, Pages: 735-739(2009)
- 作者机构：
  
  1. 中国科学院研究生院北京,100039
  2. 中国科学院长春光学精密机械与物理研究所,吉林长春 130033,E-mail:shangxc2007@hotmail.com
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN386.5
- Received：25 March 2009，
  
  Revised：02 January 1900，
  
  Published Online：30 October 2009，
  
  Published：30 October 2009
- 稿件说明：
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商小川;周辉;张星祥;任建岳. 基于FPGA的大面阵CCD高帧频驱动电路设计[J]. 液晶与显示, 2009,24(5): 735-739

SHANG Xiao-chuan;ZHOU Hui;ZHANG Xing-xiang;REN Jian-yue. Design of FPGA-Based High Frame Rate Driving Circuit for Array CCD[J]. 液晶与显示, 2009,24(5): 735-739
商小川;周辉;张星祥;任建岳. 基于FPGA的大面阵CCD高帧频驱动电路设计[J]. 液晶与显示, 2009,24(5): 735-739 DOI：

SHANG Xiao-chuan;ZHOU Hui;ZHANG Xing-xiang;REN Jian-yue. Design of FPGA-Based High Frame Rate Driving Circuit for Array CCD[J]. 液晶与显示, 2009,24(5): 735-739 DOI：

摘要

介绍了Dalsa公司的33M像素大面阵CCD的内部结构

着重分析了该款CCD的驱动时序。针对大面阵CCD图像传感器帧频较低的缺点

设计了基于现场可编程逻辑门阵列的驱动电路。改进了CCD芯片的偏置电压电路

提出了4 路同时输出以提高帧频的电路设计方法

最高帧频可达2.7帧/s

相比单端输出时的0.7帧/s提高了约4倍。选用FPGA作为核心器件

使用VHDL语言设计驱动时序

在ISE和Modelsim环境下对所设计的驱动时序发生器进行仿真实验。实验结果表明

所设计的驱动电路能够满足大面阵CCD高帧频应用。

Abstract

The inner structure of an array CCD device with 33M pixels made by Dasal corporation is introduced

and the driving schedule is analyzed in detail. Since the disadvantage of high sensitivity CCD which has lower frame rate

a design method of the full frame CCD drivers based on FPGA is put forward. To increase the frame rate by getting four outputs at the same time

the bias voltage circuit is improved. The frame rate reaches 2.7 f/s

effectively increased by about 4 times

compared with 0.7 f/s with single output. The system takes Field Programmable Gate Array (FPGA) as the key device and driving schedule generator has been described with VHDL. The designed generator has successfully fulfilled system simulation with ISE and Modelsim. It is proved that the driving system can meet the demand of the CCD in high frame rate application.

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references

. 潘松,黄继业. EDA技术与VHDL [M]. 北京:清华大学出版社,2005.

. 金龙旭,李国宁,刘妍妍,等. 帧转移型面阵CCD驱动电路的设计 [J]. 光学精密工程 ,2008,16(6):1140-1145.

. 王华伟,刘波,曹剑中,等. 基于FPGA的全帧CCD驱动设计 [J]. 电光与控制, 2007,14 (5):175-178.

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. 盛翠霞,张涛,纪晶,等. 高分辨率CCD芯片FTF4052M 的驱动系统设计 [J]. 光学精密工程, 2007,15(4):564-569.

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. 周辉,张星祥,陶宏江,等. 基于行间转移CCD场输出模式下的成像系统设计 [J]. 液晶与显示, 2009,24(1):121-125.

. 李云飞,李敏杰,司国良. TDI-CCD图像传感器的噪声分析和处理 [J]. 光学精密工程 ,2007,15(8):1196-1202.

. 刘光林,杨世洪,吴钦章,等. 高分辨率大面阵CCD相机的高帧频设计 [J]. 半导体光电 ,2007,28(5):735-738.

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