In order to reducing the damaged risk of a linearity CCD camera which was debug frequently

the CCD cameras characteristic and timing diagram were analyzed

a CCD camera simulation system was designed based on Field Programmable Gate Array(FPGA). The system made the FPGA as the core device

a Read Only Memory(ROM) was in inaugurated inside FPGA

which stored a standard image gray data

output gray data in the falling edge of pixel clock

counted the amount of pixel clock which bringed Trigger Line Readout and horizontal synchronization signal. The simulation results show the simulation process of the linearity CCD camera simulation system satisfies the demand of CCD camera timing diagram. The design of the simulation system shortens the engineering debug time

provides guarantee for evening data collection and storage.